Circuits for delay mismatch compensation and related methods

A circuit for driving a load, the circuit comprising:

• an integrated circuit comprising:
• a first contact coupled to a first connection disposed outside the integrated circuit and a second contact coupled to a second connection disposed outside the integrated circuit;
• a clock driver;
• a feedback circuit;
• a first signal path portion comprising the first contact of the integrated circuit and a first retimer;
• a first delay element coupled between the first retimer and the clock driver;
• a second signal path portion comprising the second contact of the integrated circuit and a second retimer;
• a second delay element coupled between the second retimer and the clock driver;
• and
• control circuitry configured to delay a first output signal at the first contact of the integrated circuit relative to a second output signal at the second contact of the integrated circuit by controlling the first and second delay elements;
• wherein the feedback circuit and the first delay element form a first ring oscillator and the feedback circuit and the second delay element form a second ring oscillator.

A method for driving a load disposed outside an integrated circuit, the method comprising:

• controlling a circuit to form a first ring oscillator during a first time period and sensing a first cadence of the first ring oscillator, the first ring oscillator including a portion of a first clock path, wherein the circuit is disposed on the integrated circuit and the integrated circuit comprises a first contact coupled to a first connection disposed outside the integrated circuit and a second contact coupled to a second connection disposed outside the integrated circuit;
• controlling the circuit to form a second ring oscillator during a second time period and sensing a second cadence of the second ring oscillator, the second ring oscillator including a portion of a second clock path;
• controlling the portion of the first clock path to command a timing of a portion of a first signal path and controlling the portion of the second clock path to command a timing of a portion of a second signal path to introduce a delay mismatch between a first output signal at the first contact of the integrated circuit and a second output signal at the second contact of the integrated circuit at least partially based on the first cadence and the second cadence;
• and
• driving the first signal path with the first output signal and driving the second signal path with the second output signal after the circuit is controlled to introduce the delay mismatch.