Biased amplifier
AssigneeTexas Instruments Incorporated
InventorSudheer Prasad
Life of this patent
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Abstract
In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.
Claims20
An amplifier, comprising:
- a bias circuit;
- and
- a buffer stage coupled to the bias circuit and comprising:
- a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a source terminal coupled to a second node;
- a gate terminal coupled to a third node, a drain terminal coupled to a fourth node, and a bulk connection coupled to a first node, a first resistor coupleable between the first node and the second node;
- a first n-type MOSFET (NMOS) having a drain terminal coupled to the fourth node, a gate terminal coupled to the bias circuit, and a source terminal configured to couple to a fifth node via a second resistor;
- and
- a second NMOS having a drain terminal coupled to the second node, a gate terminal coupled to the fourth node, and a source terminal coupled to the fifth node, wherein the buffer stage is configured to couple to a first capacitor and a third resistor coupled in series between the fourth node and the fifth node, and wherein the second node is an output of the amplifier.
A circuit comprising:
- an input node configured to couple to a sensor;
- an output node;
- a ground node;
- a voltage supply node;
- a bias circuit configured to generate a bias voltage;
- a buffer stage that includes:
- a first transistor that includes a gate coupled to the input node;
- a first resistor coupled to the first transistor;
- a second transistor coupled to the first transistor that includes a gate coupled to receive the bias voltage;
- a second resistor coupled between the second transistor and the ground node;
- and
- a third transistor coupled to the output node that includes a gate coupled to the first transistor and the second transistor.
A circuit comprising an input node configured to couple to a sensor;
- an output node;
- a first transistor that includes a gate coupled to the input node, a source coupled to the output node, a drain coupled to a first node, and a bulk;
- a first resistor coupled between the source of the first transistor and the bulk of the first transistor;
- a second transistor that includes a drain coupled to the first node, a gate, and a source;
- a second resistor coupled between the source of the second transistor and a ground node;
- and
- a third transistor that includes a gate coupled to the first node, a drain coupled to the output node, and a source coupled to the ground node.
Dependencies are inferred from the claim text.