Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit

A user programmable integrated circuit comprising:

• a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements;
• a plurality of matrix vector multipliers, each matrix vector multiplier including a plurality of word lines, each word line coupled to a different first one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line;
• and
• a plurality of charge-to-pulse-width converter circuits, each being associated with one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network,
• each charge-to-pulse-width converter circuit including:
• a slave current mirror section mirroring current from a master current mirror section;
• a first switch coupling a capacitor to the input of the charge-to-pulse-width converter circuit to charge the capacitor during a charge collection time frame;
• a second switch coupling the capacitor to the slave current mirror section to discharge the capacitor at a constant current during an analog pulse generating time frame;
• a comparator coupled to the capacitor to indicate when the capacitor has been discharged;
• and
• a logic gate configured to output the analog pulse during the analog pulse generating time frame until the comparator indicates that the capacitor has been discharged.