Packet transfer device and packet transfer method

A packet transfer device comprising:

• a circuit configured to include a first queue to store a first packet classified into a high priority class and a second queue to store a second packet classified into a low priority class having a lower priority than the high priority class, the circuit outputting the first packet and the second packet;
• a memory configured to store data configured to indicate possibilities of output for the first packet and the second packet for each time slot;
• and
• a processor coupled to the memory and the processor configured to:
• control the output of the first packet and the second packet for each time slot according to the data stored in the memory;
• count a number of discards of the second packet within the second queue in a predetermined cycle;
• and
• change the data stored in the memory, when the number of discards of the second packet within the second queue is less than a first predetermined value, so as to-reduce an output period of the second packet within the second queue for every time slot in the predetermined cycle by reducing a number of time slots for which the second packet is outputted according to a short order of the output period.