# US 11,018,845 B1 · Quarter-rate serial-link receiver with low-aperture-delay samplers

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- Number: US 11,018,845 B1
- Document ID: US11018845B1
- Status: Granted
- Kind: B1
- Application number: 17/046,250
- Filed: 2019-04-05
- Published: 2021-05-27
- Granted: 2021-05-25
- Earliest claimed: 2018-04-09
- Assignees: The Regents of the University of California
- Applicants: The Regents of the University of California
- Inventors: Chang Liu; Xiaoguang Liu
- Web page: https://patentgrep.com/patent/US11018845B1

## CPC

- H04L 7/0087: {Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection}
- H04L 27/38: Demodulator circuits; Receiver circuits
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)}
- H04L 25/03063: {using fractionally spaced delay lines or combinations of fractionally and integrally spaced taps}
- H04L 25/03133: {with a non-recursive structure (H04L25/03127 takes precedence)}
- H04L 25/063: {Setting decision thresholds using feedback techniques only}
- H04L 27/0014: {Carrier regulation (of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657)}
- H04L 2025/03509: {fractionally spaced (H04L2025/03515 takes precedence)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

The disclosed embodiments provide a system that implements a low-aperture-delay sampler. The system includes a sampler input, which receives an input signal, and a clock input, which receives a clock signal. The system also includes: a first sampling channel, which samples the input signal when the clock signal is low and is associated with a previous clock phase; and a second sampling channel, which samples the input signal when a rising edge is received in the clock signal, wherein the rising edge is associated with a present clock phase. The system additionally includes a combining mechanism, which combines outputs of the first and second sampling channels to produce a sampler output with a significantly reduced aperture delay.

## Claims

### Claim 1

A low-aperture-delay sampler, comprising:
a sampler input, which receives an input signal;
a clock input, which receives a clock signal;
a first sampling channel, which samples the input signal when the clock signal is low and is associated with a previous clock phase;
a second sampling channel, which samples the input signal when a rising edge is received in the clock signal, wherein the rising edge is associated with a present clock phase; and
a combining mechanism, which combines outputs of the first and second sampling channels to produce a sampler output with a significantly reduced aperture delay.

### Claim 2 (depends on 1)

The low-aperture-delay sampler of claim 1,
wherein the input is an incoming analog signal; and
wherein the low-aperture-delay sampler comprises a component in a serial-link receiver, which produces a sampled output of the incoming analog signal.

### Claim 3 (depends on 1)

The low-aperture-delay sampler of claim 1,
wherein the input is an incoming analog signal; and
wherein the low-aperture-delay sampler comprises a component in a system that supports simultaneous sampling.

### Claim 4 (depends on 3)

The low-aperture-delay sampler of claim 3, wherein the system that supports simultaneous sampling comprises one of the following:
a high-speed serializer/deserializer (SerDes) system;
a time-interleaved analog-to-digital converter (ADC) system; and
a direct l/Q demodulation system.

### Claim 5 (depends on 1)

The low-aperture-delay sampler of claim 1, further comprising a memory element, which stores an output of the first sampling channel to facilitate combining the output of the first sampling channel with a subsequently received output of the second sampling channel.

### Claim 6 (depends on 1)

The low-aperture-delay sampler of claim 1, wherein by combining samples of the input signal from the previous and present clock phases, the low-aperture-delay sampler significantly reduces aperture delay.

### Claim 7

A serial-link receiver, comprising:
a continuous-time linear equalizer (CTLE);
a decision-feedback equalizer (DFE);
a sampler;
clock-and-data-recovery (CDR) circuits, which dynamically adjust a DFE threshold and a sampler offset, wherein the CDR circuits perform calculations to determine corresponding DFE-threshold and sampler-offset adjustments in the digital domain, and then combine the DFE-threshold and sampler-offset adjustments into a combined adjustment signal; and
a digital-to-analog converter (DAC), which converts the combined adjustment signal into a corresponding analog adjustment signal, which is fed back into the serial-link receiver through a single tap.

### Claim 8 (depends on 7)

The serial-link receiver of claim 7, wherein the single tap comprises a pair of transistors coupled to a pair of differential signal lines at the output of the sampler.

### Claim 9 (depends on 7)

The serial-link receiver of claim 7, wherein feeding the combined adjustment signal back into the serial-link receiver through the single tap reduces parasitic capacitance as compared with using multiple taps, thereby increasing bandwidth and reducing power consumption.

### Claim 10 (depends on 7)

The serial-link receiver of claim 7, wherein performing the calculations in the digital domain to determine the corresponding DFE-threshold and sampler-offset adjustments enables the results of the calculations to be reused.

### Claim 11 (depends on 7)

The serial-link receiver of claim 7, wherein the sampler is a low-aperture-delay sampler, comprising:
a sampler input, which receives an input signal;
a first sampling channel, which samples the input signal when a clock signal is low and is associated with a previous clock phase;
a second sampling channel, which samples the input signal when a rising edge is received in the clock signal, wherein the rising edge is associated with a present clock phase; and
a combining mechanism, which combines outputs of the first and second sampling channels to produce a sampler output with a significantly reduced aperture delay.

### Claim 12 (depends on 11)

The serial-link receiver of claim 11, wherein the sampler further comprises a memory element, which stores an output of the first sampling channel to facilitate combining the output of the first sampling channel with a subsequently received output of the second sampling channel.

### Claim 13 (depends on 7)

The serial-link receiver of claim 7, wherein the serial-link receiver comprises a quarter-rate serial-link receiver.

### Claim 14 (depends on 13)

The serial-link receiver of claim 13,
wherein the CTLE is a quarter-rate CLTE;
wherein the DFE is a quarter-rate one-tap DFE with eight high-decision-accuracy samplers; and
wherein the CDR circuits comprise quarter-rate CDR circuits.

### Claim 15

A method for operating a low-aperture-delay sampler, comprising:
receiving an input signal;
receiving a clock signal;
feeding the input signal through a first sampling channel, which samples the input signal when a clock signal is low and is associated with a previous clock phase;
feeding the input signal through a second sampling channel, which samples the input signal when a rising edge is received in the clock signal, wherein the rising edge is associated with a present clock phase; and
combining outputs of the first and second sampling channels to produce a sampler output with a significantly reduced aperture delay.

### Claim 16 (depends on 15)

The method of claim 15, further comprising storing the output of the first sampling channel in a memory element to facilitate combining the output of the first sampling channel with a subsequently received output of the second sampling channel.

### Claim 17 (depends on 15)

The method of claim 15, wherein by combining samples of the input signal from the previous and present clock phases, the method significantly reduces aperture delay.

### Claim 18

A method for operating a serial-link receiver, which includes a CTLR, a DFE, a sampler and CDR circuits, the method comprising:
performing digital calculations to determine DFE-threshold and sampler-offset adjustments;
combining the DFE-threshold and sampler-offset adjustments into a combined adjustment signal;
using a DAC to convert the combined adjustment signal into a corresponding analog adjustment signal; and
feeding back the analog adjustment signal into the serial-link receiver through a single tap.

### Claim 19 (depends on 18)

The method of claim 18, wherein the single tap comprises a pair of transistors coupled to a differential pair of signal lines at the output of the sampler.

### Claim 20 (depends on 18)

The method of claim 18, wherein feeding the combined adjustment signal back into the serial-link receiver through the single tap reduces parasitic capacitance as compared with using multiple taps, thereby increasing bandwidth and reducing power consumption.