Differential amplifier, corresponding integrated circuit, system, instrumentation amplifier and method

A differential amplifier comprising:

• first and second input nodes configured to receive first and second input voltages, respectively;
• first and second output nodes configured to receive first and second output voltages, respectively;
• first and second supply nodes configured to receive first and second power supply voltages, respectively;
• first and second offset compensation nodes configured to receive first and second offset compensation voltages, respectively;
• a first amplifier stage configured to generate the first output voltage as a function of the first input voltage and the first offset compensation voltage;
• a second amplifier stage configured to generate the second output voltage as a function of the second input voltage and the second offset compensation voltage;
• and
• a feedback circuit configured to generate the first offset compensation voltage and the second offset compensation voltage as a function of the first and the second output voltages, wherein the feedback circuit comprises:
• a coupling circuit coupled between the first and second offset compensation nodes, or
• first and second terminals coupled to the first and second offset compensation nodes, respectively, wherein the first and second terminals are configured to be coupled to a coupling circuit external to the differential amplifier, wherein the coupling circuit comprises one or more passive electric components, wherein the feedback circuit comprises:
• a first bias current source;
• a second bias current source;
• a fifth transistor having a current path coupled between the first bias current source and a first node, and a control terminal coupled to the first output node;
• a sixth transistor having a current path coupled between the first node and the first supply node, and a control terminal coupled to the first offset compensation node;
• a seventh transistor having a current path coupled between the second bias current source and a second node, and a control terminal coupled to the second output node;
• and
• an eighth transistor having a current path coupled between the second node and the first supply node, and a control terminal coupled to the second offset compensation node.

An integrated circuit comprising a differential amplifier that comprises:

• first and second input nodes configured to receive first and second input voltages, respectively;
• first and second output nodes configured to receive first and second output voltages, respectively;
• first and second supply nodes configured to receive first and second power supply voltages, respectively;
• first and second offset compensation nodes configured to receive first and second offset compensation voltages, respectively;
• a first amplifier stage configured to generate the first output voltage as a function of the first input voltage and the first offset compensation voltage;
• a second amplifier stage configured to generate the second output voltage as a function of the second input voltage and the second offset compensation voltage;
• and
• a feedback circuit configured to generate the first offset compensation voltage and the second offset compensation voltage as a function of the first and the second output voltages, wherein the feedback circuit comprises:
• first and second coupling nodes configured to be coupled to each other via a resistor in parallel with a capacitor, the first and second coupling node coupled to the first and second offset compensation nodes, respectively.

A method of reducing a DC offset in a differential amplifier, the method comprising:

• receiving first and second input voltages with first and second input nodes of the differential amplifier, respectively;
• receiving a first and second supply voltages with first and second power supply nodes of the differential amplifier, respectively;
• receiving first and second offset compensation voltages with first and second offset compensation nodes of the differential amplifier, respectively, wherein the first and second offset compensation nodes are directly connected to each other via a capacitor;
• generating first and second output voltages at first and second output nodes of the differential amplifier, respectively, with first and second amplifier stages, respectively, wherein generating the first and second output voltages comprises generating the first and second output voltages based on the first and second input voltages and the first and second offset compensation nodes;
• and
• generating the first and second offset compensation voltages based on the first and second output voltages, wherein a first transistor has a current path coupled between the first power supply node and the first output node, and a control terminal directly connected to the first offset compensation node, and wherein a second transistor has a current path coupled between the first power supply node and the second output node, and a control terminal directly connected to the second offset compensation node.

A differential amplifier comprising:

• first and second input nodes configured to receive first and second input voltages, respectively;
• first and second output nodes configured to receive first and second output voltages, respectively;
• first and second supply nodes configured to receive first and second power supply voltages, respectively;
• a bias current source coupled to the second supply node;
• a first transistor having a control terminal coupled to the first input node, a first current path terminal coupled to the bias current source, and a second current path terminal coupled to a first intermediate node that is coupled to the first output node;
• a second transistor having a first current path terminal coupled to the first intermediate node, and a second current path terminal coupled to the first supply node;
• a third transistor having a control terminal coupled to the second input node, a first current path terminal coupled to the bias current source, and a second current path terminal coupled to a second intermediate node that is coupled to the second output node;
• a fourth transistor having a first current path terminal coupled to the second intermediate node, and a second current path terminal coupled to the first supply node;
• a resistor directly connected between a control terminal of the second transistor and a control terminal of the fourth transistor;
• and
• a feedback circuit having a first input coupled to the first output node, a second input coupled to the second output node, a first output coupled to a third intermediate node between the control terminal of the second transistor and the resistor, and a second output coupled to a fourth intermediate node between the control terminal of the fourth transistor and the resistor.