Using Fuzzy-Jbit location of floating-point multiply-accumulate results
AssigneeIntel Corporation
InventorsAmit Gradstein, Simon Rubanovich, Zeev Sperber
Life of this patent
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AssigneeIntel Corporation
InventorsAmit Gradstein, Simon Rubanovich, Zeev Sperber
Estimating the term…
Disclosed embodiments relate to performing floating-point (FP) arithmetic. In one example, a processor is to decode an instruction specifying locations of first, second, and third floating-point (FP) operands and an opcode calling for accumulating a FP product of the first and second FP operands with the third FP operand, and execution circuitry to, in a first cycle, generate the FP product having a Fuzzy-Jbit format comprising a sign bit, a 9-bit exponent, and a 25-bit mantissa having two possible positions for a JBit and, in a second cycle, to accumulate the FP product with the third FP operand, while concurrently, based on Jbit positions of the FP product and the third FP operand, determining an exponent adjustment and a mantissa shift control of a result of the accumulation, wherein performing the exponent adjustment concurrently enhances an ability to perform the accumulation in one cycle.
A processor comprising:
A method to be performed by a processor, the method comprising:
A non-transitory machine-readable medium containing instructions to which a processor is to respond by:
Dependencies are inferred from the claim text.