Encoding and decoding architecture for high speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof

A physical layer circuit at a transmitter, comprising:

• an encoding chain, configured to encode a plurality of symbols to generate a plurality of first wire states, the encoding chain comprising:
• a plurality of encoding units coupled in series, arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively, wherein a first encoding unit of the encoding units is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit of the encoding units;
• and
• a plurality of first flip-flops, coupled to the encoding units to receive the first wire states respectively, the first flip-flops being arranged to output the first wire states according to a first clock signal, respectively, wherein one of the first flip-flops is coupled between the first encoding unit and the second encoding unit, and the second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the first flip-flops;
• the one of the first flip-flops is arranged to output the second wire state in a clock cycle of the first clock signal before the first flip-flops are arranged to output the first wire states in another clock cycle of the first clock signal.