Clock recovery based on digital signals
AssigneeSony Corporation
InventorJacob Adams Wysocki
Life of this patent
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Abstract
A clock recovery circuit includes a first pulse circuit, a second pulse circuit, a state change circuit connected to the first pulse circuit and the second pulse circuit and a first delay circuit connected to the state change circuit and each of the first pulse circuit and the second pulse circuit. The first pulse circuit receives data inputs to generate a first pulse signal. The second pulse circuit receives the data inputs to generate a second pulse signal. The state change circuit receives the first pulse signal and the second pulse signal and generate a first clock signal for a first transition of one of the data inputs in a first unit interval (UI). The first delay circuit receives the generated first clock signal and mask other transitions of the data inputs in the first UI.
Claims21
A clock recovery circuit, comprising:
- a first pulse circuit configured to receive a plurality of data inputs to generate a first pulse signal;
- a second pulse circuit configured to receive the plurality of data inputs to generate a second pulse signal;
- a state change circuit connected to the first pulse circuit and the second pulse circuit, wherein the state change circuit is configured to
- receive the first pulse signal and the second pulse signal, and
- generate a first clock signal for a first transition of one of the plurality of data inputs in a first unit interval (UI), based on the generated first pulse signal and the second pulse signal;
- and
- a first delay circuit connected to the state change circuit and each of the first pulse circuit and the second pulse circuit, wherein the first delay circuit is configured to
- receive the generated first clock signal, and
- mask other transitions, different from the first transition, of the plurality of data inputs in the first UI.
An electronic device, comprising:
- a clock recovery circuit which includes:
- a first pulse circuit configured to receive a plurality of data inputs to generate a first pulse signal;
- a second pulse circuit configured to receive the plurality of data inputs to generate a second pulse signal;
- a state change circuit connected to the first pulse circuit and the second pulse circuit, wherein the state change circuit is configured to:
- receive the first pulse signal and the second pulse signal, and
- generate a first clock signal for a first transition of one of the plurality of data inputs in a first unit interval (UI), based on the generated first pulse signal and the second pulse signal;
- and
- a first delay circuit connected to the state change circuit and each of the first pulse circuit and the second pulse circuit, wherein the first delay circuit is configured to:
- receive the generated first clock signal, and
- mask other transitions, different from the first transition, of the plurality of data inputs in the first UI.
A method, comprising:
- in a clock recovery circuit:
- receiving, via a first pulse circuit, a plurality of data inputs to generate a first pulse signal;
- receiving, via a second pulse circuit, the plurality of data inputs to generate a second pulse signal;
- generating, by a state change circuit connected to the first pulse circuit and the second pulse circuit, a first clock signal for a first transition of one of the plurality of data inputs in a first unit interval (UI) based on the first pulse signal and the second pulse signal;
- and
- receiving, by a first delay circuit connected to the state change circuit and each of the first pulse circuit and the second pulse circuit, the generated first clock signal to mask other transitions, different from the first transition, of the plurality of data inputs in the first UI.
Dependencies are inferred from the claim text.