High radix subset code multiplier architecture
AssigneeIntel Corporation
InventorsMartin Langhammer, Gregg Baeckler
Life of this patent
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Abstract
Systems, methods, and devices for enhancing performance/efficiency of soft multiplier implementations are provided. More specifically, a method to implement soft multipliers with a high radix subset code architecture is provided. The techniques provided herein result in smaller multipliers that consume less area, improve packing, consume less power, and improve routing options on an integrated circuit.
Claims20
A programmable logic device, comprising:
- a multiplier coding, comprising one or more coded multiplier values;
- and
- a multiplier configured to perform a multiplication operation based on the multiplier coding for each of the one or more coded multiplier values corresponding to a value between negative three and positive three, inclusive, wherein the multiplier skips implementation for a subset of the one or more coded multiplier values, wherein the subset comprises at least one coded multiplier value corresponding to a value less than negative three, greater than positive three, or both, wherein the multiplier comprises two look-up tables for each bit of a multiplicand to be multiplied by a coded multiplier value.
A tangible, non-transitory, machine-readable medium, comprising machine-readable instructions that, when executed by one or more processors, cause the one or more processors to:
- generate a program describing a hardware implementation for a multiplier;
- cause the multiplier to be implemented on programmable logic of a programmable logic device, wherein the multiplier, when implemented on the programmable logic device:
- is configured to perform a multiplication operation based on one or more coded multiplier values of a plurality of coded multiplier values for each of the one or more coded multiplier values corresponding to a value between negative three and positive three, inclusive, wherein the multiplier skips implementation of the multiplication operation for a subset of the plurality of coded multiplier values, wherein the subset comprises at least one coded multiplier value corresponding to a value less than negative three, greater than positive three, or both;
- and
- comprises a plurality of additional multipliers each configured to generate a partial product.
A method, comprising:
- decoding a set of multiplier values based on a multiplier coding;
- and
- performing a multiplication operation via multiplier circuitry based on the set of multiplier values for each multiplier value of the set of multiplier values corresponding to a value between negative three and positive three, inclusive, wherein the multiplier circuitry skips implementation for a subset of the multiplier values, wherein the subset comprises at least one multiplier value corresponding to a value less than negative three, greater than positive three, or both, wherein the multiplier circuitry comprises two look-up tables for each bit of a multiplicand to be multiplied by a multiplier value.
Dependencies are inferred from the claim text.