Read/write direction-based memory bank control for imaging

A memory control system comprising:

• a memory having a plurality of banks;
• and
• a memory control apparatus for controlling the memory, the memory control apparatus including a processor configured to function as
• a transmitting/receiving unit that receives a write request data set and a read request data set, the write request data set including write data and requesting writing of data into the memory, the read request data set requesting reading of data from the memory, and transmits read data that is read corresponding to the read request;
• a processing priority data generating unit that generates processing priority data that represents a priority of processing in controlling the memory;
• a branching unit that divides a write destination of the write data for respective predetermined areas in the memory, and divides a read destination of the read data for respective predetermined areas in the memory, the predetermined areas each being a row in any one bank among the plurality of banks;
• a buffer control unit that attaches the processing priority data and transfer IDs to generate write control data for the respective predetermined areas by using the write request data set and the processing priority data, and attaches the processing priority data and transfer IDs to generate read control data for the respective predetermined areas by using the read request data set and the processing priority data;
• a write buffer that temporarily stores the write data;
• inside-bank arbitration queues included by the plurality of banks, the inside-bank arbitration queues storing the write control data and the read control data;
• an arbitration unit that executes an arbitration that determines a priority order of processing taking the write control data and the read control data that are stored in the arbitration queue as targets;
• a command generating unit that writes the write data stored in the write buffer into the memory by using the write control data selected based on the priority order, and generates a command to temporarily store read data read from the memory in a read buffer by using the read control data selected based on the priority order;
• and
• a change processing unit that changes the processing priority data every time a predetermined time elapses;
• wherein
• the arbitration unit
• raises a priority order taking the write control data or the read control data that includes the processing priority data as a timeout request when the processing priority data has passed a preliminarily set threshold by the change,
• determines whether a control direction status of the memory is a write-side status or a read-side status,
• selects the write control data in preference to the read control data in the respective plurality of inside-bank arbitration queues when the control direction status of the memory is determined to be the write-side status,
• selects the read control data in preference to the write control data in the respective plurality of inside-bank arbitration queues when the control direction status of the memory is determined to be the read-side status, and
• determines the control direction status based on the selected read control data and write control data.

A memory control system comprising:

• a memory having a plurality of banks;
• and
• a memory control apparatus for controlling the memory, the memory control apparatus including a processor configured to function as
• a transmitting/receiving unit that receives a write request data set and a read request data set, the write request data set including write data and requesting writing of data into the memory, the read request data set requesting reading of data from the memory, and transmits read data that is read corresponding to the read request;
• a processing priority data generating unit that generates processing priority data that represents a priority of processing in controlling the memory;
• a branching unit that divides a write destination of the write data for respective predetermined areas in the memory, and divides a read destination of the read data for respective predetermined areas in the memory, the predetermined areas each being a row in any one bank among the plurality of banks;
• a buffer control unit that attaches the processing priority data and transfer IDs to generate write control data for the respective predetermined areas by using the write request data set and the processing priority data, and attaches the processing priority data and transfer IDs to generate read control data for the respective predetermined areas by using the read request data set and the processing priority data;
• a write buffer that temporarily stores the write data;
• an arbitration queue that stores the write control data and the read control data;
• an arbitration unit that executes an arbitration that determines a priority order of processing taking the write control data and the read control data that are stored in the arbitration queue as targets;
• a command generating unit that writes the write data stored in the write buffer into the memory by using the write control data selected based on the priority order, and generates a command to temporarily store read data read from the memory in a read buffer by using the read control data selected based on the priority order;
• a change processing unit that changes the processing priority data every time a predetermined time elapses;
• and
• an overlap address detecting unit that detects overlap access request data that is a write request data set or a read request data set that requests an access to an address that is at least partially overlapping an address of a write destination of received write request data set or a read destination of received read request data set, the overlap address detecting unit identifying the bank among the plurality of banks where the overlap access request data requests the access;
• wherein
• the arbitration unit
• raises a priority order taking the write control data or the read control data that includes the processing priority data as a timeout request when the processing priority data has passed a preliminarily set threshold by the change in the change processing unit, and
• stops the arbitration of the bank identified by the overlap address detecting unit.