Microprocessor for neural network computing and processing method of macroinstruction

A microprocessor for neural network computing, comprising:

• a mapping table and a microcode memory, wherein according to the mapping table, a macroinstruction is mapped to an address on the microcode memory;
• a microcode decoding finite-state machine (FSM), decoding contents which are retrieved from the microcode memory according to the address, to get microinstructions involving at least one microinstruction loop that is repeated to operate a datapath to complete the macroinstruction;
• and
• registers, storing at least a bit width of the datapath,
• wherein:
• the bit width is dynamically adjusted in the registers according to statistics of a plurality of calculation results of a plurality of calculations of the datapath;
• the microcode decoding finite-state machine further decodes and obtains information about the macroinstruction;
• the information about the macroinstruction includes a size of a source operand indicated by the macroinstruction and a size of input operands of the datapath and, accordingly, the microcode decoding finite-state machine divides the source operand into the input operands;
• and
• the size of the input operands depends on the dynamically adjusted bit width acquired from the registers.