High-density low voltage non-volatile differential memory bit-cell with shared plate-line

A system comprising:

• an artificial intelligence processor;
• and
• a non-volatile memory coupled to the artificial intelligence processor, wherein the non-volatile memory includes differential bit-cells, wherein one of the differential bit-cell includes:
• a first transistor having a gate terminal coupled to a word-line (WL) and one of a source or drain terminal coupled to a first bit-line (BL);
• a second transistor having a gate terminal coupled to the WL and one of a source or drain terminal coupled to a second bit-line (BLB), wherein the BLB is to provide a signal which is inverse of a signal on BL;
• a first non-volatile structure coupled to one of the drain or source of the first transistor, and further coupled to a plate-line (PL);
• and
• a second non-volatile structure coupled to one of the drain or source of the second transistor, and further coupled to the PL;
• wherein each of the first and second non-volatile structures comprises:
• a first layer comprising a first refractive inter-metallic material, wherein the first layer is adjacent to the drain or source of the first or second transistor;
• a second layer comprising a first conductive oxide, wherein the second layer is adjacent to the first layer;
• a third layer comprising a perovskite material, wherein the third layer is adjacent to the second layer;
• a fourth layer comprising a second conductive oxide, wherein the fourth layer is adjacent to the third layer;
• a fifth layer comprising a second refractive inter-metallic material, wherein the fifth layer is adjacent to the PL and adjacent to the fourth layer;
• a sixth layer directly adjacent to first sides of the first, second, third, fourth and fifth layers;
• and
• a seventh layer directly adjacent to second sides of the first, second, third, fourth and fifth layers, wherein the sixth and the seventh layers comprise a barrier material.

A method for forming a differential bit-cell, the method comprising:

• fabricating a first transistor having a gate terminal coupled to a word-line (WL) and one of a source or drain terminal coupled to a first bit-line (BL);
• fabricating a second transistor having a gate terminal coupled to the WL and one of a source or drain terminal coupled to a second bit-line (BLB), wherein the BLB is to provide a signal which is inverse of a signal on BL;
• forming a first ferroelectric structure coupled to one of the drain or source of the first transistor, and further coupled to a plate-line (PL);
• and
• forming a second ferroelectric structure coupled to one of the drain or source of the second transistor, and further coupled to the PL, wherein the first and second ferroelectric structures comprise a perovskite material;
• wherein forming the first or second ferroelectric structures comprises:
• forming a first layer comprising a first refractive inter-metallic material, wherein the first layer is adjacent to the drain or source of the first or second transistor;
• forming a second layer comprising a first conductive oxide, wherein the second layer is adjacent to the first layer;
• forming a third layer comprising a perovskite material, wherein the third layer is adjacent to the second layer;
• forming a fourth layer comprising a second conductive oxide, wherein the fourth layer is adjacent to the third layer;
• forming a fifth layer comprising a second refractive inter-metallic material, wherein the fifth layer is adjacent to the PL and adjacent to the fourth layer;
• forming a sixth layer adjacent to a first side of the first, second, third, fourth and fifth layers;
• forming a sixth layer directly adjacent to first sides of the first, second, third, fourth and fifth layers;
• and
• forming a seventh layer directly adjacent to second sides of the first, second, third, fourth and fifth layers, wherein the sixth and the seventh layers comprise a barrier material.