Low drop-out (LDO) voltage regulator circuit

A low drop-out (LDO) voltage regulator circuit, comprising:

• a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node;
• a current regulation loop configured to sense current flowing through the power transistor and modulate the control signal to cause the power transistor to output a constant current to the output node;
• and
• a voltage regulation loop configured to sense voltage at the output node and modulate the control signal to cause the power transistor to deliver current to the output node so that an output voltage at the output node is regulated;
• wherein the current regulation loop comprises a control transistor having a first conduction terminal connected to the control terminal of the power transistor and having a control terminal driven by a signal that depends on a difference between the sensed current flowing through the power transistor and a reference;
• wherein the voltage regulation loop comprises:
• a differential input circuit having a first input configured to receive the voltage sensed at the output node and a second input configured to receive a voltage regulation reference voltage;
• and
• a gain circuit having an input coupled to an output of the differential input circuit and an output configured to generate the control signal for application to the control terminal of the power transistor;
• wherein the gain circuit includes a capacitor having a capacitance to set a pole at a frequency that does not exceed a zero at the output node.

A low drop-out (LDO) voltage regulator circuit, comprising:

• a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node;
• a current regulation loop configured to sense current flowing through the power transistor and modulate the control signal to cause the power transistor to output a constant current to the output node;
• and
• a voltage regulation loop configured to sense voltage at the output node and modulate the control signal to cause the power transistor to deliver current to the output node so that an output voltage at the output node is regulated;
• wherein the current regulation loop comprises a control transistor having a first conduction terminal connected to the control terminal of the power transistor and having a control terminal driven by a signal that depends on a difference between the sensed current flowing through the power transistor and a reference;
• wherein the voltage regulation loop comprises:
• a differential input circuit having a first input configured to receive the voltage sensed at the output node and a second input configured to receive a voltage regulation reference voltage;
• a first amplifier circuit having an input coupled to an output of the differential input circuit, the first amplifier circuit configured to generate a first control signal;
• a second amplifier circuit having an input coupled to the output of the differential input circuit, the second amplifier circuit configured to generate a second control signal;
• and
• an analog multiplexer circuit having a first input configured to receive the first control signal and a second input configured to receive the second control signal, wherein the analog multiplexer circuit selectively passes one of the first and second control signals as the control signal applied to the control terminal of the power transistor in response to a select signal.