Low-power, low-noise millimeter wavelength frequency synthesizer

The system of 2, wherein the locking status can be one of the following:

• the SSPLL output signal is properly locked to a harmonic of the IF signal;
• the SSPLL output signal is improperly locked to a harmonic of the reference signal, which is not a harmonic of the IF signal;
• and
• the SSPLL output signal is not locked to any signal.

A method for operating a frequency synthesizer, comprising:

• feeding a reference signal into an intermediate-frequency (IF) synthesizer, which generates an IF signal based on the reference signal;
• feeding the IF signal and the reference signal into a switch, which is configured to select either the reference signal or the IF signal to be an input signal to a sub-sampling phase-locked loop (SSPLL), which generates a high-frequency output signal based on the input signal;
• wherein when the reference signal is the input signal to the SSPLL, the frequency synthesizer operates in a low-noise normal-operating mode in which the frequency synthesizer can become unlocked from a desired target frequency;
• an
• wherein when the IF signal is the input signal to the SSPLL, the frequency synthesizer operates in a higher-noise, frequency-acquisition mode in which the frequency synthesizer automatically locks to the target frequency;
• feeding the IF signal and the high-frequency output signal into a sub-sampling lock detector (SSLD);
• and
• operating the SSLD, which involves,
• determining whether the frequency synthesizer becomes unlocked from the target frequency during the normal-operating mode, and if so, activating the switch to move the frequency synthesizer into the frequency-acquisition mode, and
• determining whether the frequency synthesizer becomes relocked to the target frequency during the frequency-acquisition mode, and if so, activating the switch to move the frequency synthesizer into the normal-operating mode.

The method of 12, wherein the locking status can be one of the following:

• the SSPLL output signal is properly locked to a harmonic of the IF signal;
• the SSPLL output signal is improperly locked to a harmonic of the reference signal, which is not a harmonic of the IF signal;
• and
• the SSPLL output signal is not locked to any signal.

An apparatus that includes a frequency synthesizer, comprising:

• an electronic system that uses a high-frequency output signal produced by the frequency synthesizer to control various operations performed by the electronic system;
• the frequency synthesizer, which is coupled to an electronic system, wherein the frequency synthesizer comprises:
• an intermediate-frequency (IF) synthesizer that generates an IF signal based on a reference signal;
• a sub-sampling phase-locked loop (SSPLL) that generates the high-frequency output signal based on an input signal;
• a switch, which is configured to select either the reference signal or the IF signal to be the input signal to the SSPLL, wherein when the reference signal is the input signal to the SSPLL, the frequency synthesizer operates in a low-noise normal-operating mode in which the frequency synthesizer can become unlocked from a desired target frequency, and when the IF signal is the input signal to the SSPLL, the frequency synthesizer operates in a higher-noise, frequency-acquisition mode in which the frequency synthesizer automatically locks to the target frequency;
• and
• a sub-sampling lock detector (SSLD), which is configured to:
• determine whether the frequency synthesizer becomes unlocked from the target frequency during the normal-operating mode, and if so, to activate the switch to move the frequency synthesizer into the frequency-acquisition mode, and
• determine whether the frequency synthesizer becomes relocked to the target frequency during the frequency-acquisition mode, and if so, to activate the switch to move the frequency synthesizer into the normal-operating mode.