# US 10,992,301 B1 · Circuit and method for generating temperature-stable clocks using ordinary oscillators

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,992,301 B1
- Document ID: US10992301B1
- Status: Granted
- Kind: B1
- Application number: 16/816,113
- Filed: 2020-03-11
- Granted: 2021-04-27
- Earliest claimed: 2020-01-09
- Assignees: Microsemi Semiconductor ULC
- Applicants: Microsemi Semiconductor ULC
- Inventors: Krste Mitric; Kamran Rahbar
- Web page: https://patentgrep.com/patent/US10992301B1

## CPC

- H03L 1/027: {by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/subtract logic circuit (H03L1/023, H03L1/026 take precedence)}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/07: using several loops, e.g. for redundant clock signal generation
- H03L 7/0994: {comprising an accumulator}
- H03L 7/22: using more than one loop
- H03L 2207/50: All digital phase-locked loop
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A circuit for generating temperature-stable clocks including first and second crystal oscillators, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to the first and second crystal oscillators, a second phase acquisition circuit coupled to the input for the reference clock source and to the second crystal oscillator, a first DPLL coupled to the first phase acquisition circuit, a crystal oscillator variation estimator coupled to the first DPLL, a second DPLL coupled to the second phase acquisition circuit and including a phase-frequency detector having a input coupled to the second phase acquisition circuit, a loop filter, a frequency subtractor having an input coupled to the loop filter and an input coupled to the crystal oscillator variation estimator, and a DCO coupled to the frequency subtractor and driving an input of the phase-frequency detector.

## Claims

### Claim 1

A circuit for generating a temperature-stable clock comprising:
a first crystal oscillator;
a second crystal oscillator;
an input for a reference clock source;
a clock output;
a first phase acquisition circuit coupled to an output of the first crystal oscillator and to an output of the second crystal oscillator;
a second phase acquisition circuit coupled to the input for the reference clock source and to an output of the second crystal oscillator;
a first digital phase locked loop (DPLL) coupled to an output of the first phase acquisition circuit;
a crystal oscillator variation estimator coupled to an output of the first DPLL; and
a second DPLL coupled to an output of the second phase acquisition circuit, the second DPLL including:
a phase-frequency detector having a first input coupled to the output of the second phase acquisition circuit;
a loop filter;
a frequency subtractor having a first input coupled to an output of the loop filter and a second input coupled to an output of the crystal oscillator variation estimator; and
a digital controlled oscillator (DCO) coupled to an output of the frequency subtractor, an output of the DCO coupled to a second input of the phase-frequency detector and coupled to the clock output.

### Claim 2 (depends on 1)

The circuit of claim 1 further comprising a synthesizer coupled to the output of the DCO and driving the clock output.

### Claim 3 (depends on 1)

The circuit of claim 1 wherein the DCO is a software DCO.

### Claim 4 (depends on 1)

The circuit of claim 1 wherein the first crystal oscillator and the second crystal oscillator are disposed in a single package.

### Claim 5 (depends on 1)

The circuit of claim 1 wherein the crystal oscillator variation estimator includes a multiplier having one input coupled to the output of the first DPLL and a second input coupled to a memory storing polynomial coefficients generated during initial production and characterization of the first and second crystal oscillators obtained by curve fitting of frequency variations of the second crystal oscillator over temperature versus frequency differences between the first and second crystal oscillators.

### Claim 6 (depends on 5)

The circuit of claim 5 where the memory is one of a non-volatile memory and a one-time-programmable memory.

### Claim 7 (depends on 5)

The circuit of claim 5 wherein the first crystal oscillator, the second crystal oscillator, and the memory are disposed in a single package.

### Claim 8 (depends on 1)

The circuit of claim 1 wherein the crystal oscillator variation estimator includes a multiplier having one input coupled to the output of the first DPLL and a second input coupled to a memory storing polynomial coefficients generated during initial production and characterization of the first and second crystal oscillators obtained by curve fitting of frequency variations of the second crystal oscillator over temperature versus frequency differences between the first and second crystal oscillators.

### Claim 9 (depends on 1)

The circuit of claim 1 wherein the first DPLL is a high bandwidth DPLL and the second DPLL is a low bandwidth DPLL.

### Claim 10 (depends on 1)

The circuit of claim 1 wherein the loop filter has one of 1st and 2nd order low pass characteristics.

### Claim 11

A method for generating temperature-stable clocks comprising:
providing first and second crystal oscillators;
providing a memory that stores temperature characterization polynomial coefficients generated during initial production and characterization of the first and second crystal oscillators obtained by curve fitting frequency variations of the second crystal oscillator over temperature versus frequency differences between the first and second crystal oscillators over temperature;
measuring the phase difference between the first crystal oscillator and the second crystal oscillator;
phase locking a high-bandwidth first digital phase locked loop (DPLL) to the measured phase difference between the first crystal oscillator and the second crystal oscillator;
estimating frequency variations of the second crystal oscillator responsive to frequency information based on the measured phase difference, and responsive to the stored temperature characterization polynomial coefficients;
providing a reference clock signal from a reference clock source;
measuring the phase difference between the reference clock signal and the second crystal oscillator;
phase locking a second DPLL to the phase difference between the reference clock signal and the second crystal oscillator;
adjusting the frequency of the second DPLL by the estimated frequency variation of the second crystal oscillator; and
providing an output from the second DPLL.

### Claim 12 (depends on 11)

The method of claim 11 further comprising providing the output of the second DPLL to a frequency synthesizer.

### Claim 13 (depends on 11)

The method of claim 11 wherein the providing first and second crystal oscillators comprises providing first and second crystal oscillators in the same package.

### Claim 14 (depends on 11)

The method of claim 11 wherein the measuring the phase difference between the first crystal oscillator and the second crystal oscillator comprises measuring the phase difference between the first crystal oscillator and the second crystal oscillator in a first phase acquisition circuit.

### Claim 15 (depends on 11)

The method of claim 11 wherein the measuring the phase difference between the reference clock signal and the second crystal oscillator comprises measuring the phase difference between the reference clock signal and the second crystal oscillator in a second phase acquisition circuit.

### Claim 16 (depends on 11)

The method of claim 11 wherein the adjusting the frequency of the second DPLL by the estimated frequency variation over temperature of the second crystal oscillator comprises adjusting the frequency of the second DPLL using a frequency subtractor circuit.

### Claim 17 (depends on 11)

The method of claim 11 wherein providing the output of the second DPLL comprises providing the output of the second DPLL from a digitally controlled oscillator in the second DPLL.

### Claim 18 (depends on 17)

The method of claim 17 further comprising providing the output of the digitally controlled oscillator to a synthesizer.