Hysteresis comparator

A hysteresis comparator, comprising:

• an input stage, configured to receive a pair of differential input signals to generate at least one differential current signal;
• a hysteresis current generating circuit, configured to generate at least one hysteresis current to adjust the differential current signal to generate an adjusted differential current signal, wherein the hysteresis current generating circuit comprises a common mode voltage detecting circuit to detect a common mode voltage of the differential input signals for generating the at least one hysteresis current;
• and
• an output stage, configured to generate an output signal according to the adjusted differential current signal;
• wherein the input stage receives the differential input signals to generate two differential current signals, and the input stage comprises:
• a first current source;
• two first N-type transistors, wherein the respective sources of the two first N-type transistors are coupled to the first current source, and each of the two first N-type transistors receives the differential input signals in order to generate one of the two differential current signals at the drain thereof;
• a second current source;
• and
• two first P-type transistors, wherein the sources of the two first P-type transistors are coupled to the second current source, and each of the two first P-type transistors receives the differential input signals in order to generate the other of the two differential current signals at the drain thereof;
• wherein the hysteresis current generating circuit generates two hysteresis currents of the at least one hysteresis current to adjust the two differential current signals to generate two adjusted differential current signals, and the common mode voltage detecting circuit in the hysteresis current generating circuit comprises:
• two second N-type transistors, configured to receive the differential input signals to generate one of the two hysteresis currents, for adjusting one of the two differential current signals;
• and
• two second P-type transistors, configured to receive the differential input signals to generate the other of the two hysteresis currents, for adjusting the other of the two differential current signals;
• wherein the hysteresis current generating circuit comprises:
• two third N-type transistors, wherein the two third N-type transistors are respectively controlled by the output signal and an inverse signal of the output signal, the sources of the two third N-type transistors are coupled to each other and are coupled to the drains of the two second N-type transistors, the drain of one of the two third N-type transistors is coupled to the drain of one of the two first N-type transistors, and the drain of the other of the two third N-type transistors is coupled to a reference voltage;
• and
• two third P-type transistors, wherein the two third P-type transistors are respectively controlled by the output signal and the inverse signal of the output signal, the sources of the two third P-type transistors are coupled to each other and are coupled to the drains of the two second P-type transistors, and the drain of one of the two third P-type transistors is coupled to the drain of one of the two first P-type transistors, and the drain of the other of the two third P-type transistors is coupled to another reference voltage.