Video processing system using ring buffer and racing-mode ring buffer access control scheme

A video processing system comprising:

• a storage device, comprising:
• a data buffer;
• a bitstream buffer;
• and
• a display buffer;
• a receiving circuit, arranged to receive packets and unpack the packets to write payload data of the packets into the data buffer;
• an audio/video demultiplexing circuit, arranged to fetch an input data from the data buffer, and perform an audio/video demultiplexing operation upon the fetched input data to write data of a video bitstream into the bitstream buffer, wherein the fetched input data comprise payload data of at least one of the packets;
• a video decoder, arranged to fetch data of the video bitstream from the bitstream buffer, and perform a video decoding operation upon the fetched data of the video bitstream to write pixel data of a reconstructed video frame into the display buffer;
• and
• a display engine, arranged to fetch pixel data of the reconstructed video frame from the display buffer, and drive a display device according to the fetched pixel data of the reconstructed video frame;
• wherein the data buffer is a ring buffer coupled between the receiving circuit and the audio/video demultiplexing circuit, the bitstream buffer is a ring buffer coupled between the audio/video demultiplexing circuit and the video decoder, and the display buffer is a ring buffer coupled between the video decoder and the display engine;
• wherein the video decoder comprises a first counter arranged to maintain a first count value indicative of a number of pixel lines that are reconstructed by the video decoder;
• the first counter adjusts the first count value each time one coding block row is completely decoded, where said one coding block row includes pixels in a column direction;
• the display engine comprises a second counter arranged to maintain a second count value indicative of a number of pixel lines that are displayed on the display device through the display engine;
• the second counter adjusts the second count value each time one pixel line is completely displayed;
• and the video processing system further comprises:
• a display control circuit, arranged to receive the first count value from the video decoder, receive the second count value from the display engine, compare the first count value with the second count value, and instruct the video decoder to stop writing pixel data of the reconstructed video frame into the display buffer when a distance between the first count value and the second count value reaches a threshold.