US 10,983,756 B2Granted

Small multiplier after initial approximation for operations with increasing precision

AssigneeImagination Technologies Limited

InventorLeonard Rarick

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Abstract

In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor. The full-precision multiplier circuit requires a first number of clock cycles to complete, and both the small multiplier and the initial approximation circuitry complete within the first number of clock cycles.

Claims12

Dependent claims

An apparatus for executing an instruction requesting an arithmetic operation on an operand by an input value by performing an iterative arithmetic operation on said input value to obtain an output value that is used to represent a result of executing said instruction, the apparatus comprising:

initial approximation circuitry configured in hardware to provide, from at least a portion of said input value, an initial approximation of said output value, the initial approximation of the output value having a second number of bits of precision that is less than a first number of bits of precision to which said output value is to be produced;
limited precision multiplier circuitry configured in hardware to receive the initial approximation and multiply the initial approximation with another value to obtain a first multiplication result;
full-precision multiplier circuitry coupled to receive the first multiplication result from the limited precision multiplier circuitry and configured in hardware to multiply the first multiplication result from the limited precision multiplier circuitry with another value to obtain a second multiplication result on which said output value is based, the second multiplication result having no fewer than the first number of bits of precision, wherein the full-precision multiplier circuitry requires a first number of clock cycles to finish its multiplication, and a combined number of clock cycles required by the initial approximation circuitry to provide the initial approximation and the limited precision multiplier circuitry to complete a multiplication is equal to or less than the first number of clock cycles;
and
an output configured in hardware to output said output value representing the result of executing said instruction.

2 more elements

initial approximation circuitry configured in hardware to provide, from at least a portion of said input value, an initial approximation of said output value, the initial approximation of the output value having a second number of bits of precision that is less than a first number of bits of precision to which said output value is to be produced;
limited precision multiplier circuitry configured in hardware to receive the initial approximation and multiply the initial approximation with another value to obtain a first multiplication result;
full-precision multiplier circuitry coupled to receive the first multiplication result from the limited precision multiplier circuitry and configured in hardware to multiply the first multiplication result from the limited precision multiplier circuitry with another value to obtain a second multiplication result on which said output value is based, the second multiplication result having no fewer than the first number of bits of precision, wherein the full-precision multiplier circuitry requires a first number of clock cycles to finish its multiplication, a combined number of clock cycles required by the initial approximation circuitry to provide the initial approximation and the limited precision multiplier circuitry to complete a multiplication is equal to or less than the first number of clock cycles;
an output configured in hardware to output said output value representing the result of executing said instruction;
and
wherein the full-precision multiplier circuitry is further configured to feed the second multiplication result back as an input to the full-precision multiplier circuitry to iteratively refine said output value.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/516,643Filed 17 Oct 2014
Published: US 2016/0110163 A121 Apr 2016
Granted: 20 Apr 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 7/552
For evaluating functions by calculation: powers or roots , e.g. Pythagorean sums
G06F 7/523
Multiplying; Dividing: multiplying only
G06F 7/537
Dividing only: reduction of the number of iteration steps or stages, e.g. using the Sweeny-Robertson-Tocher [SRT] algorithm
G06F 7/5525
Powers or roots , e.g. Pythagorean sums: roots or inverse roots of single operands