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US 10,978,487 B2Granted
Inverting circuit
AssigneesSTMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.
InventorsHassan El Dirani, Pascal Fonteneau
Life of this patent
Estimating the term…
Abstract
An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.
Claims26
An inverter comprising:
- a semiconductor substrate;
- a Z2-FET switch disposed at a first surface of the semiconductor substrate, wherein the Z2-FET comprises a first anode, a first cathode, a first front gate, a first back gate, and a second back gate;
- and
- a further switch disposed at the first surface of the semiconductor substrate, wherein the further switch comprises a second anode, a second cathode, a second front gate, a third back gate, and a fourth back gate, wherein the first back gate and the third back gate are coupled to a first reference potential and the second back gate and the fourth back gate are coupled to a second reference potential, the further switch having a current path between the anode and the cathode of the further switch coupled in series with a current path between the anode and the cathode of the Z2-FET switch between a first reference terminal and a second reference terminal.
1 more element
An inverter comprising:
- an N-type Z2-FET switch having a cathode coupled to an inverter output terminal, an anode coupled to a positive reference terminal, a top gate coupled to an inverter input terminal, and a back gate having a P-type doped portion coupled to a positive potential and an N-type doped portion coupled to a negative potential;
- and
- a P-type Z2-FET switch having a cathode connected to the cathode of the N-type Z2-FET switch and the inverter output terminal, an anode coupled to a negative reference terminal, a top gate coupled to the inverter input terminal, and a back gate having a P-type doped portion coupled to the positive potential and the N-type doped portion coupled to a negative potential.
An inverter comprising:
- a silicon on insulator substrate having a semiconductor layer overlying an insulating layer that overlies a semiconductor substrate;
- a first Z2-FET switch having an anode region disposed in the semiconductor layer, a cathode region disposed in the semiconductor layer, a P-type doped region disposed in the semiconductor layer between the anode region and the cathode region, an insulated gate region positioned on top of and in contact with a portion of the P-type doped region, and a back gate disposed in the semiconductor substrate beneath the anode region, cathode and P-type doped region;
- a second Z2-FET switch having an anode region disposed in the semiconductor layer, a cathode region disposed in the semiconductor layer, a P-type doped region disposed in the semiconductor layer between the anode region and the cathode region, an insulated gate region positioned on top of and in contact with a portion of the P-type doped region, and a back gate disposed in the semiconductor substrate beneath the anode region, cathode and P-type doped region;
- an input terminal coupled to the gate region of the first Z2-FET switch and to the gate region of the second Z2-FET switch;
- an output terminal coupled to the cathode region of the first Z2-FET switch and to the cathode region of the second Z2-FET switch;
- a first reference terminal coupled to the anode region of the first Z2-FET switch;
- and
- a second reference terminal coupled to the anode region of the second Z2-FET switch.
5 more elements
An inverter comprising:
- an N-type Z2-FET switch disposed at a first surface of a semiconductor substrate, wherein the Z2-FET comprises a P-type anode region, an N-type cathode region, a P-type intermediate region disposed between the P-type anode region and the N-type cathode region, a front gate disposed over the P-type intermediate region, a first back gate comprising a P-type doped portion, and a second back gate comprising a N-type doped portion, the first back gate being coupled to a negative reference potential node and the second back gate being coupled to a positive reference potential node;
- and
- an N-channel MOS transistor disposed at the first surface of the semiconductor substrate, the N-channel MOS transistor having a gate, the N-channel MOS transistor being coupled between the N-type cathode region of the N-type Z2-FET switch and a reference potential node, the P-type anode region coupled to a supply voltage node, the gate of the N-channel MOS transistor and the front gate of the N-type Z2-FET switch being coupled to an input voltage node.
Dependencies are inferred from the claim text.