US 10,978,470 B2Granted

Semiconductor device including multiple layers of memory cells, method of manufacturing the same, and electronic device including the same

AssigneeInstitute of Microelectronics, Chinese Academy of Sciences

InventorHuilong Zhu

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Abstract

The memory device includes multiple stacked layers of memory cells. Each of the layers includes a first array of first memory cells and a second array of second memory cells, which are nested with each other. The first memory cells and the second memory cells in the respective layers are substantially aligned to each other in a stacking direction of the memory cell layers. Each of the first memory cells is a vertical device based on a first source/drain layer, a channel layer, and a second source/drain layer stacked. Each of the second memory cells is a vertical device based on an active semiconductor layer extending in the stacking direction. The first and second memory cells include respective storage gate stacks, which share a common gate conductor layer. Gate conductor layers in the same memory cell layer are integral with each other.

Claims34

Dependent claims

A memory device, comprising:

multiple layers of memory cells which are stacked on a substrate in sequence, wherein each of the multiple layers of memory cells comprises a first array of first memory cells and a second array of second memory cells,
wherein the first array and the second array are nested with each other, the respective first memory cells in the respective layers of memory cells are substantially aligned to each other in a stacking direction of the layers of memory cells, and the respective second memory cells in the respective layers of memory cells are substantially aligned to each other in a stacking direction of the layers of memory cells, and
wherein each of the first memory cells comprises:
a first source/drain layer, a channel layer, and a second source/drain layer which are stacked in sequence, wherein the channel layer comprises a semiconductor material different from that of the first and second source/drain layers;
and
a first storage gate stack formed to surround a periphery of the channel layer,
wherein gate conductor layers in the respective first storage gate stacks in the same layer of memory cells are integral with each other, and
wherein for each of the first memory cells, the first source/drain layer thereof is integral with the second source/drain layer of a corresponding first memory cell at a lower layer, and the second source/drain layer thereof is integral with the first source/drain layer of a corresponding first memory cell at an upper layer,
wherein each of the second memory cells comprises:
an active semiconductor layer;
and
a second storage gate stack formed to surround a periphery of the active semiconductor layer,
wherein for each of the second memory cells, the active semiconductor layer thereof extends integrally with the respective active semiconductor layers of a corresponding second memory cell at a lower layer and a corresponding second memory cell at an upper layer, and
wherein in the same layer of memory cells, the first storage gate stacks and the second storage gate stacks comprise a common gate conductor layer.

11 more elements

A method of manufacturing a memory device, comprising:

providing a stack of source/drain layers and channel layers alternatively stacked on a substrate, wherein the lowermost layer of the stack is a source/drain layer, and the uppermost layer of the stack is a source/drain layer;
forming a number of machining holes in the stack;
selectively etching the channel layers in the stack through the machining holes, to form an array of multiple cell channel portions, which are separated from each other, in each of the channel layers of the stack;
forming storage gate stacks for first memory cells in gaps in the stack through the machining holes;
removing materials left after the selectively etching the channel layers in the machining holes to expose the machining holes;
selectively etching the source/drain layers in the stack through the machining holes, to form cell source/drain portions respectively on upper and lower sides of each of the cell channel portions, wherein each of the cell channel portions and the cell source/drain portions on upper and lower sides thereof form a corresponding one of the first memory cells;
forming an isolation layer in gaps in the stack through the machining holes;
removing materials left after the forming the isolation layer in the machining holes to expose the machining holes;
and
forming storage gate stacks for second memory cells on sidewalls of the machining holes, and filling an active semiconductor layer for the second memory cells in the machining holes of which the sidewalls have the storage gate stacks for the second memory cells formed thereon.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/338,212Filed 31 Mar 2017
Priority: CN 201610872740.330 Sep 2016
Published: US 2020/0027897 A123 Jan 2020
Granted: 13 Apr 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification32 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10D 30/63
Insulated-gate field-effect transistors [IGFET]: vertical IGFETs
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 53/20
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the three-dimensional [3D] arrangements, e.g. with…