Partially and fully parallel normaliser
AssigneeImagination Technologies Limited
InventorTheo Alan Drane
Life of this patent
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Abstract
Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalisation block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.
Claims12
Hardware logic arranged to normalize or renormalize a binary number, the hardware logic comprising:
- a zero counter arranged to determine a number of leading or trailing zeros in the binary number;
- and
- shifting logic arranged to perform shifting of the binary number;
- wherein at least a portion of the shifting is performed without input from the zero counter.
A method of normalizing or renormalizing a binary number, the method comprising:
- determining, by hardware logic, a number of leading or trailing zeros in the binary number in a zero counter;
- and
- shifting the binary number in shifting logic, and wherein at least a portion of the shifting is performed without input from the zero counter.
A non-transitory computer readable storage medium having stored thereon computer executable program code that when executed causes at least one processor to
- determine a number of leading or trailing zeros in a binary number in a zero counter;
- and
- shifting the binary number, wherein at least a portion of the shifting is performed without input from the zero counter.
Dependencies are inferred from the claim text.