Processor with reconfigurable pipelined core and algorithmic compiler
AssigneeIcat LLC
InventorRobert Catiller
Life of this patent
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Abstract
An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a system. The reusable algorithmic pipelined core is a reconfigurable processing core with a pipelined structure comprising a processor with a setup interface for programming any of a plurality of operations as determined by setup data, a logic decision processor for programming a look up table, a loop counter and a constant register, and a block of memory. This can be used to perform functions. A reconfigurable, programmable circuit routes data and results from one core to another core and/or IO controller and/or interrupt generator, as required to complete an algorithm without further intervention from a central or peripheral processor during processing of an algorithm.
Claims14
A precompiler comprises an algorithmic matching pipelined compiler, wherein the algorithmic matching pipelined compiler comprises a processing unit, and the algorithmic matching pipelined compiler is configured to precompile a standard higher level software language written for a type of conventional non-reconfigurable processor, and the algorithmic matching pipelined compiler generates machine code for one or more reusable cores by using the processing unit, wherein the machine code provides instructions for configuring the one or more reusable cores, such that the one or more reusable cores are capable of being configured or reconfigured to independently solve complex mathematical and logic algorithms without further intervention by the processing unit after the algorithmic matching pipelined compiler configures the one or more reusable cores, wherein the processing unit is disposed on a chip.
A method of using a precompiler comprises an algorithmic matching pipelined compiler with a processing unit, the method comprising:
- precompiling, by the processing unit, a standard higher level software language written for a type of conventional non-reconfigurable processor;
- generating, by the processing unit, machine code for one or more reusable cores, wherein the machine code provides instructions for configuring the one or more reusable cores, such that the one or more reusable cores are configured or reconfigured to independently solve complex mathematical and logic algorithms without further intervention by the processing unit after the algorithmic matching pipelined compiler configures the one or more reusable cores;
- and
- independently solving complex mathematical and logic algorithms without further intervention by the processing unit using only the one or more reusable cores as configured or reconfigured by the precompiler.
Dependencies are inferred from the claim text.