Programmable multiply-add array hardware
AssigneeAlibaba Group Holding Limited
InventorsLiang Han, Xiaowei Jiang
Life of this patent
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Abstract
An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.
Claims18
A method for operating a data architecture including N adders and N multipliers configured to operate in one of a multiply-reduce mode or a multiply-accumulate mode, the method comprising:
- selecting a data flow between the N multipliers and the N adders of the data architecture, wherein the N multipliers and at least some of the N adders of the data architecture are used both in the multiply-reduce mode and the multiply-accumulate mode and wherein the data architecture is configured to change a connection between the N multipliers and the N adders according to the selected data flow, and
- operating the data architecture in one of the multiply-reduce mode or the multiply-accumulate mode according to the selected data flow.
An integrated circuit comprising:
- a data architecture including N adders and N multipliers, wherein the data architecture is configured to operate in one of a multiply-reduce mode or a multiply-accumulate mode according to a selected data flow between the N multipliers and the N adders of the data architecture and wherein the data architecture is configured to change a connection between the N multipliers and the N adders according to the selected data flow, the selected data flow comprises:
- a first data flow associated with the multiply-accumulate mode;
- and
- a second data flow associated with the multiply-reduce mode,
- wherein the N multipliers and the at least some of the N adders are used both in the first data flow and the second data flow.
A non-transitory computer-readable storage medium that stores a set of instructions that is executable by at least one processor of a device to cause the device to perform a method for operating a data architecture including N adders and N multipliers configured to operate in one of a multiply-reduce mode or a multiply-accumulate mode, the method comprising:
- selecting a data flow between the N multipliers and the N adders of the data architecture, wherein the N multipliers and at least some of the N adders of the data architecture are used both in the multiply-reduce mode and the multiply-accumulate mode and wherein the data architecture is configured to change a connection between the N multipliers and the N adders according to the selected data flow, and
- operating the data architecture in one of the multiply-reduce mode or the multiply-accumulate mode according to the selected data flow.
Dependencies are inferred from the claim text.