Zero hold time sampler for low voltage operation

A differential sampling circuit for a serializer/deserializer (SerDes) receiver, comprising:

• a latching circuit having differential inputs, differential outputs, a clocked input circuit coupled to the differential inputs, a first cross-coupled circuit coupled to the clocked input circuit, and a second cross-coupled circuit coupled to the first cross-coupled circuit, wherein the first and second cross-coupled circuits are coupled to the differential outputs of the latching circuit;
• a plurality of pass-gate transistors, each pass-gate transistor coupled between one of the differential inputs of the latching circuit and a corresponding differential input of the sampling circuit;
• a voltage rail configured to supply current to the sampling circuit;
• and
• a plurality of capacitive elements, each capacitive element coupled between the voltage rail and a node coupled to the one of the differential inputs of the latching circuit and to a corresponding pass-gate transistor.