High bandwidth under-sampled successive approximation register analog to digital converter with nonlinearity minimization

A method comprising:

• sampling, by a sampling switch triggered by a sampling clock in an under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC), an input signal;
• determining, by a comparator in the under-sampled SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the under-sampled SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths;
• resampling, by the sampling switch, the input signal for each successive bit;
• determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit;
• and
• outputting, by a digital controller in the under-sampled SAR ADC, a digital result after determining a value for a last bit by the comparator.

A device comprising:

• a first under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) including a first data path and a first reference path matched for minimizing circuit disturbances, the first under-sampled SAR ADC configured to sample a first input signal of a different input pair using a first sampling clock, perform a step in a regression process to determine a bit value based on the sampled first input signal and a reference signal, resample the first input signal for a successive step using the first sampling clock, perform the successive step to determine another bit value based on the resampled first input signal and another reference signal, and output a digital result when the regression process is complete;
• a second under-sampled SAR ADC including a second data path and a second reference path matched for minimizing circuit disturbances, the second under-sampled SAR ADC configured to sample a second input signal of a different input pair using a second sampling clock, perform a step in a regression process to determine a bit value based on the sampled second input signal and a reference signal for the second under-sampled SAR ADC, resample the second input signal for a successive step for the second under-sampled SAR ADC using the second sampling clock, perform the successive step for the second under-sampled SAR ADC to determine another bit value based on the resampled second input signal and another reference signal for the second under-sampled SAR ADC, and output a second digital result when the regression process is complete;
• and
• a controller configured to generate a differential output based on the digital result and the second digital result.