Digital-to-analog converter and electronic system including the same

A digital-to-analog converter (DAC) comprising:

• a current array including a plurality of unit cells, the plurality of unit cells being arranged in a matrix formation including a plurality of rows and a plurality of columns;
• an arbitrary switch box configured to change an arrangement order of bits based on a random number;
• and
• processing circuitry configured to
• generate (2M+1) first bits based on an upper M bits of a digital input signal of N bits, N being an integer greater than or equal to two and M being an integer less than N,
• generate a plurality of first column selection signals and a plurality of second column selection signals based on a plurality of randomized first bits, the plurality of randomized first bits being obtained from the arbitrary switch box based on the (2M+1) first bits,
• generate 2(N−M) row selection signals based on a lower (N−M) bits of the digital input signal,
• randomly select a subset of columns among the plurality of columns based on the plurality of first column selection signals, the subset of columns including first unit cells among the plurality of unit cells,
• randomly select one column among the plurality of columns based on the plurality of second column selection signals,
• select a subset of rows among the plurality of rows based on the 2(N−M) row selection signals, second unit cells among the plurality of unit cells being included in both the one column and the subset of rows, and
• generate an analog output signal corresponding to the digital input signal based on the first unit cells and the second unit cells.

An electronic system comprising:

• a first digital-to-analog converter (DAC) configured to generate a first analog output signal based on a first digital input signal, wherein the first digital-to-analog converter includes
• a current array including a plurality of unit cells, the plurality of unit cells being in a matrix formation including a plurality of rows and a plurality of columns,
• an arbitrary switch box configured to change an arrangement order of bits based on a random number, and
• processing circuitry configured to
• generate (2M+1) first bits based on an upper M bits among the first digital input signal of N bits, N being an integer greater than or equal to two and M being an integer less than N,
• generate a plurality of first row selection signals and a plurality of second row selection signals based on a plurality of randomized first bits, the plurality of randomized first bits being obtained from the arbitrary switch box based on (2M+1) first bits,
• generate 2(N−M) column selection signals based on a lower (N−M) bits of the first digital input signal,
• randomly select a subset of rows among the plurality of rows based on the plurality of first row selection signals, the subset of rows including first unit cells among the plurality of unit cells,
• randomly select one row among the plurality of rows based on the plurality of second row selection signals,
• select a subset of columns among the plurality of columns based on the 2(N−M) column selection signals, second unit cells among the plurality of unit cells being included in both the one row and the subset of columns, and
• generate the first analog output signal based on the first unit cells and the second unit cells.