Deglitching circuit and method in class-D amplifier
AssigneeSTMicroelectronics (Shenzhen) R&D Co. Ltd
InventorsRu Feng Du, Qi Yu Liu
Life of this patent
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Abstract
In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.
Claims22
A class-D amplifier comprising:
- an input terminal configured to receive an input signal;
- a comparator having an input coupled to the input terminal;
- a deglitching circuit having an input coupled to an output of the comparator;
- and
- a driving circuit having an input coupled to an output of the deglitching circuit, wherein the deglitching circuit comprises a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit, the logic circuit configured to receive a clock signal having a same frequency as a switching frequency of the class-D amplifier, wherein the logic circuit comprises a second input configured to receive the clock signal, and wherein the deglitching circuit is configured to produce at the output of the deglitching circuit:
- a 0 when the input is 0 and the second input is 0;
- a 1 when the input is 1 and the second input is 1;
- and
- keep a previous state of the output of the deglitching circuit when the input is 0 and the second input is 1 or when the input is 1 and the second input is 0.
A class-D amplifier comprising:
- a fully-differential pre-amplifier circuit having first and second input terminals configured to receive an input signal and first and second output terminals configured to generate an amplified signal based on the input signal;
- a first integrator having an input terminal coupled to the first output terminal of the fully-differential pre-amplifier circuit;
- a second integrator having an input terminal coupled to the second output terminal of the fully-differential pre-amplifier circuit;
- a first comparator having an input terminal coupled to an output terminal of the first integrator;
- a second comparator having an input terminal coupled to an output terminal of the first integrator;
- first and second deglitching circuits having input terminals coupled to output terminals of the first and second comparators, respectively;
- and
- first and second driving circuits having input terminals coupled to output terminals of the first and second deglitching circuits, respectively, wherein each of the first and second deglitching circuits comprise:
- a first deglitching input terminal configured to receive a first signal,
- a deglitching output terminal, and
- a logic circuit coupled between the first deglitching input terminal and the deglitching output terminal, the logic circuit comprising a latch.
A method of deglitching in an audio class-D amplifier, the method comprising:
- receiving an input signal with the audio class-D amplifier;
- generating a first signal based on the input signal;
- comparing the first signal with a reference signal to generate a pulse-width modulation (PWM) signal;
- deglitching the PWM signal to produce a deglitched PWM signal;
- and
- driving an output stage of the audio class-D amplifier with the deglitched PWM signal, wherein deglitching the PWM signal comprises:
- receiving a clock signal,
- setting the deglitched PWM signal to a first state when the PWM has the first state and the clock signal has the first state,
- setting the deglitched PWM signal to a second state when the PWM has the second state and the clock signal has the second state, and
- keeping a same state of the deglitched PWM signal when the PWM signal has the first state and the clock signal has the second state, or when the PWM signal has the second state and the clock signal has the first state.
Dependencies are inferred from the claim text.