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US 10,965,261 B2Granted
Power amplifier circuit
AssigneeQUALCOMM Incorporated
InventorsJeremy Dunworth, Hyunchul Park, Bon-Hyun Ku, Vladimir Aparin
Life of this patent
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Abstract
The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.
Claims28
An amplifier circuit comprising:
- one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration, comprising:
- an NMOS transistor having a gate terminal electrically coupled to an input node configured to receive an input signal, a source terminal electrically coupled to ground, and a drain terminal electrically coupled to a first supply voltage through a first inductive impedance element;
- and
- a PMOS transistor having a gate terminal electrically coupled to the input node, a source terminal electrically coupled to a second supply voltage, and a drain terminal electrically coupled to ground through a second inductive impedance element, the NMOS transistor electrically coupled in parallel to the PMOS transistor;
- and
- an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration comprising one or more NMOS transistors or PMOS transistors.
3 more elements
An amplifier circuit comprising:
- a first amplifier stage comprising a first path electrically coupled to one or more input nodes and a second path electrically coupled to the one or more input nodes, the first amplifier stage comprising one or more first PMOS transistors in the first path and one or more first NMOS transistors in the second path;
- a second amplifier stage comprising a first path electrically coupled to the first path of the first amplifier stage and comprising one or more second NMOS transistors in the first path, the second amplifier stage comprising a second path electrically coupled to the second path of the first amplifier stage and comprising one or more second PMOS transistors in the second path;
- and
- an output amplifier stage electrically coupled to the second amplifier stage and further electrically coupled to both the first path and the second path to form a common path for the output amplifier stage, the output amplifier stage comprising a non-complementary transistor configuration.
1 more element
An amplifier circuit comprising:
- one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration, comprising:
- a first NMOS transistor having a gate terminal electrically coupled to a first input node configured to receive a first input signal of a differential signal, a source terminal electrically coupled to ground, and a drain terminal electrically coupled to a first supply voltage through a first inductive impedance element;
- a first PMOS transistor having a gate terminal electrically coupled to the first input node, a source terminal electrically coupled to a second supply voltage, and a drain terminal electrically coupled to ground through a second inductive impedance element, the first NMOS transistor electrically coupled in parallel to the first PMOS transistor;
- a second NMOS transistor having a gate terminal electrically coupled to a second input node configured to receive a second input signal of the differential signal, a source terminal electrically coupled to ground, and a drain terminal electrically coupled to the first supply voltage through a third inductive impedance element;
- and
- a second PMOS transistor having a gate terminal electrically coupled to the second input node, a source terminal electrically coupled to the second supply voltage, and a drain terminal electrically coupled to ground through a fourth inductive impedance element;
- and
- an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration, the output amplifier stage comprising:
- a third NMOS transistor having a gate terminal electrically coupled to outputs of the first NMOS transistor and the first PMOS transistor of one of the one or more amplifier stages, a drain terminal electrically coupled to an output transformer, and a source terminal electrically coupled to ground;
- and
- a fourth NMOS transistor having a gate terminal electrically coupled to outputs of the second NMOS transistor and the second PMOS transistor of the one of the one or more amplifier stages, a drain terminal electrically coupled to the output transformer, and a source terminal electrically coupled to ground.
8 more elements
Dependencies are inferred from the claim text.