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US 10,964,702 B2Granted
Semiconductor device with first-in-first-out circuit
AssigneeMicron Technology, Inc.
InventorsSeiji Narui, Yuki Ebihara
Life of this patent
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Abstract
Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.
Claims20
An apparatus comprising:
- an input terminal supplied with an input signal;
- first and second latches coupled in series between the input terminal and a first node, the first latch configured to be controlled by a first input pointer signal, and the second latch configured to be controlled by a second input pointer signal;
- third and fourth latches coupled in series between the input terminal and a second node, the third latch configured to be controlled by a third input pointer signal, the fourth latch configured to be controlled by a fourth input pointer signal, a phase of the third input pointer signal being different from a phase of the first input pointer signal, and a phase of the fourth input pointer signal being different from a phase of the second input pointer signal;
- a first circuit coupled to the first node and configured to be controlled by a first output pointer signal;
- and
- a second circuit coupled to the second node and configured to be controlled by a second output pointer signal, a phase of the second output pointer signal being different from a phase of the first output pointer signal.
3 more elements
An apparatus comprising:
- a first plurality of FIFO circuits configured to receive a plurality of corresponding bits of data, a first input pointer signal, a second input pointer signal and a first output pointer signal, and further configured to provide a plurality of corresponding bits of first latched data responsive to the first input pointer signal, the second input pointer signal and the first output pointer signal;
- a second plurality of FIFO circuits configured to receive the plurality of corresponding bits of data and a third input pointer signal, a fourth input pointer signal and a second output pointer signal, and further configured to provide a plurality of corresponding bits of second latched data responsive to the third input pointer signal, the fourth input pointer signal and the second output pointer signal;
- and
- a data bus inversion (DBI) calculator circuit configured to receive the plurality of corresponding bits of the first latched data and the plurality of corresponding bits of the second latched data, and further configured to provide a current DBI calculation result signal,
- wherein each FIFO circuit of the first plurality of FIFO circuits includes:
- an input circuit configured to receive a corresponding bit of the data and the first and second input pointer signals, and further configured to latch the corresponding bit of the data responsive to the first input pointer signal and the second input pointer signal to provide a corresponding bit of the first latched data;
- a bit inverter configured to receive the corresponding bit of the first latched data and the current DBI calculation result signal, and configured to provide the corresponding bit of the first latched data with or without inversion as a bit inverter output signal responsive to the current DBI calculation result signal;
- and
- a logic circuit coupled to the bit inverter, and configured to provide the bit inverter output signal responsive to the first output pointer signal.
6 more elements
An apparatus comprising:
- a data bus inversion (DBI) circuit configured to receive a string of input data including first input data, second input data following the first input data and third input data following the second input data, and further configured to provide a string of output data including first output data and second output data following the first output data, the DBI circuit including:
- a first circuit including:
- a first plurality of first latch circuits on a first plurality of lanes configured to latch the first input data responsive to a first input pointer signal;
- a first plurality of second latch circuits on the first plurality of lanes configured to latch a first selected data responsive to a second input pointer signal;
- and
- a first plurality of logic circuits on the first plurality of lanes configured to provide the first output data responsive to a first output pointer signal;
- a second circuit including:
- a second plurality of first latch circuits on a second plurality of lanes configured to latch the second input data responsive to a third input pointer signal;
- a second plurality of second latch circuits on the second plurality of lanes configured to latch a second selected data responsive to a fourth input pointer signal;
- and
- a second plurality of logic circuits on the second plurality of lanes configured to provide the second output data responsive to a second output pointer signal;
- and
- a DBI calculator circuit configured to perform first DBI calculation on the latched first selected data and the latched second selected data responsive to the second latch circuit latching the first selected data and the second latch circuit latching the second selected data, respectively.
10 more elements
Dependencies are inferred from the claim text.