Techniques in phase-lock loop configuration in a computing device
AssigneeIntel Corporation
InventorsAriel Gur, Daniel J. Ragland, Yoav Ben-Raphael, Ernest Knoll
Life of this patent
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Abstract
Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.
Claims23
An apparatus for controlling a phase lock loop (PLL), the apparatus comprising:
- a digitally-controlled oscillator (DCO) and a post-DCO divider (PDIV), coupled in the PLL;
- a PLL configuration unit coupled to the PDIV, to determine a PDIV threshold value corresponding to a target PLL reference frequency, wherein the PLL configuration unit is to control operation of the PDIV based on the PDIV threshold value, wherein, to control operation of the PDIV based on the PDIV threshold value, the PLL configuration unit is further to:
- determine a PDIV value corresponding to the determined PDIV threshold value;
- and
- configure PDIV control circuitry with the determined PDIV value to divide a DCO operating frequency to produce a target PLL output frequency;
- and
- the PDIV control circuitry coupled to the PLL configuration unit and the PDIV, the PDIV control circuitry to configure a set of registers with the determined PDIV threshold value.
An apparatus for controlling a phase lock loop (PLL), the apparatus comprising:
- a digitally-controlled oscillator (DCO) and a post-DCO divider (PDIV), coupled in the PLL;
- a PLL configuration unit coupled to the PDIV, to determine a PDIV threshold value corresponding to a target PLL reference frequency, wherein the PLL configuration unit is to control operation of the PDIV based on the PDIV threshold value;
- and
- PDIV control circuitry coupled to the PLL configuration unit and the PDIV, the PDIV control circuitry to configure a set of registers with the determined PDIV threshold value, wherein the PDIV control circuitry is to configure the determined PDIV threshold value to a plurality of sets of registers corresponding to respective PLLs.
A system for a phase lock loop (PLL) reference clock reset, comprising:
- a PLL to deliver a PLL output frequency for one or more computing cores, the PLL including a digitally-controlled oscillator (DCO) and a post-DCO divider (PDIV) coupled in the PLL;
- a PLL configuration unit coupled to the PDIV via PDIV control circuitry, to receive a message to indicate a PDIV threshold value, the PDIV threshold value to indicate a minimum PLL ratio N corresponding to a PDIV value of 1 associated with a minimum DCO oscillating frequency, wherein the PLL configuration unit is further to generate a signal to indicate a completion of the configuration of the PDIV threshold value for a basic input/output system (BIOS);
- and
- the PDIV control circuitry coupled to the PLL configuration unit, the PDIV control circuitry to configure a set of registers with the received PDIV threshold value.
One or more non-transitory, computer-readable media (NTCRM) comprising instructions to, upon execution of the instructions by one or more processors of an apparatus, cause the apparatus to:
- determine a reconfiguration of a phase-lock loop (PLL) based on a target PLL reference frequency;
- determine a threshold value for a post digitally-controlled oscillator divider (PDIV) of the PLL based on the target PLL reference frequency, wherein operation of the PDIV is controlled based on the threshold value;
- configure a set of registers of PDIV control circuitry with the determined threshold value;
- determine a PDIV value corresponding to the determined threshold value and a PLL ratio for a feedback divider of the PLL, the PDIV value to be used for dividing a digitally-controlled oscillator (DCO) operating frequency to provide a target PLL output frequency;
- and
- configure the PDIV with the PDIV value.
Dependencies are inferred from the claim text.