Delay based comparator
AssigneeTexas Instruments Incorporated
InventorsRishi Soundararajan, Visvesvaraya Pentakota
Life of this patent
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Abstract
A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.
Claims7
A delay circuit having inputs for a clock signal, a positive input signal, a negative input signal, a positive reference signal and a negative reference signal, the positive input signal and the negative input signal are differential signals and the positive reference signal and the negative reference signal are differential signals, the delay circuit comprising:
- a first inverter coupled to a first transistor and a second transistor, the first inverter has a first intermediate delayed clock signal input and a positive delayed clock signal output;
- a second inverter coupled to a third transistor and a fourth transistor, the second inverter has a second intermediate delayed clock signal input and a negative delayed clock signal output;
- the first transistor has a resistance and is connected to the positive input signal, the positive input signal effects the resistance of the first transistor;
- the second transistor has a resistance and is connected to the negative reference signal, the negative reference signal effects the resistance of the second transistor;
- the third transistor has a resistance and is connected to the negative input signal, the negative input signal effects the resistance of the third transistor;
- the fourth transistor has a resistance and is connected to the positive reference signal, the positive reference signal effects the resistance of the fourth transistor;
- and
- a pair of cross-coupled capacitors coupled to the first and second inverters.
A delay circuit for delaying a clock input signal by a delay value, the delay circuit comprising:
- a complementary analog voltage input having a positive analog voltage input and a negative analog voltage input;
- a complementary reference voltage input having a positive reference voltage input and a negative reference voltage input;
- a delayed clock output;
- and
- wherein the delay value is determined based on a difference between the complementary analog voltage input and the complementary reference voltage input.
Dependencies are inferred from the claim text.