Jitter attenuation buffer structure

An electronic system comprising:

• a clock signal chain having a CML stage, the CML stage further comprising:
• a bandpass filter further comprising:
• a differential pair of FETs of a first type comprising a first FET of the first type and a second FET of the first type to receive a differential input, the first FET of the first type and the second FET of the first type each having a source coupled to separate high impedance current sources in a tail resistor generator, the first FET of the first type having a drain coupled to a plus phase of a differential output and the second FET of the first type having a drain coupled to a minus phase of the differential output;
• a capacitive source degeneration capacitor coupled between the sources of the first and second FETs of the first type;
• a first adjustable active inductor coupled to the plus phase of the differential output;
• a second adjustable active inductor coupled to the minus phase of the differential output
• the CML stage further comprising:
• the first adjustable active inductor circuit further comprises:
• a first FET of a second type biased in a saturated region, a drain of the first FET of the second type coupled to the plus phase of the differential output and a source coupled to a supply voltage;
• a first variable resistor coupled between the plus phase of the differential output and a gate of the first FET of the second type;
• a first capacitor coupled between the gate of the first FET of the second type and the minus phase of the differential output;
• the second adjustable active inductor circuit further comprises:
• a second FET of the second type biased in a saturated region, a drain of the second FET of the second type coupled to the minus phase of the differential output;
• a second variable resistor coupled between the minus phase of the differential output and a gate of the second FET of the second type;
• and
• a second capacitor coupled between the gate of the second FET of the second type and the plus phase of the differential output;
• and
• the first and second variable resistors are controlled by a control voltage to adjust a peak frequency in a bandpass filter transfer function of the bandpass filter.

A method comprising:

• creating a clock signal chain comprising a current mode logic (CML) stage, the CML stage being symmetric;
• implementing a bandpass filter in the CML stage having a bandpass filter transfer function to attenuate frequencies lower than and higher than a carrier frequency, using adjustable active inductor peaking and capacitive source degeneration;
• implementing a FET of a first type operating in linear region for a variable resistor to enable a control voltage to adjust a peak amplitude frequency of the bandpass filter transfer function;
• and
• implementing the adjustable active inductor to comprise a FET of the first type operating in a saturated region, the variable resistor, and a capacitor, the capacitor coupled to a gate of the FET of the first type operating in the saturated region and to an output on an opposite symmetrical side of the CML stage.