US 10,957,392 B2Granted

2D and 3D sum-of-products array for neuromorphic computing system

AssigneeMacronix International Co., Ltd.

InventorsFeng-Min Lee, Yu-Yu Lin

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Abstract

An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

Claims13

Dependent claims

A device, comprising a plurality of levels of word lines overlying a substrate, a plurality of vertical channel structures orthogonal to the substrate, extending through the plurality of levels of word lines, an array of variable resistance cells disposed at cross points of word lines in the plurality of levels of word lines and vertical channel structures in the plurality of vertical channel structures, the array of variable resistance cells being arranged in a plurality of vertical serially-connected strings of variable resistance cells along vertical channel structures in the plurality of vertical channel structures, at least some of the variable resistance cells in the array each comprising a programmable threshold transistor and a resistor connected in parallel;

and
circuitry to apply current to a selected vertical channel structure in the plurality of vertical channel structures, and input voltages representing values X1 to Xm of an input vector, where m is at least 3, in parallel to word lines WL1 to WLm in the plurality of levels of word lines, and
sense amplifier circuits configured for connection to the selected vertical channel structure in the plurality of vertical channel structures, which are responsive to voltage generated by the current and to a sum of variable resistances of a vertical serially-connected string of variable resistance cells along the selected vertical channel structure generated by the input voltages representing values X1 to Xm and weights stored in the variable resistance cells to produce sum-of-products results for the selected vertical channel structure.

A device, comprising:

a plurality of levels of word lines overlying a substrate;
a plurality of vertical strings of variable resistance cells orthogonal to the substrate, extending through the levels of word lines;
variable resistance cells in at least some of the strings in the plurality of vertical strings each having a first current-carrying node in a corresponding vertical channel structure of the plurality of vertical strings, a second current-carrying node in the corresponding vertical channel structure, and a control terminal in a corresponding word line of the plurality of levels of word lines, and comprising a programmable threshold transistor and a resistor connected in parallel to the first and second current-carrying nodes, the programmable threshold transistor having a gate connected to the control terminal;
and wherein:
a variable resistance of each of the variable resistance cells in the strings is a function of a voltage applied to the control gate of the cell, a threshold of the programmable threshold transistor, and the resistor;
and including
circuitry to apply current to a selected vertical string in the plurality of vertical strings, and input voltages representing values X1 to Xm of an input vector, where m is at least 3, in parallel to word lines WL1 to WLm in the plurality of levels of word lines, and
sense amplifier circuits configured for connection to the selected vertical string in the plurality of vertical strings, which are responsive to voltage generated by the current and to a sum of variable resistances of the variable resistance cells along the selected vertical string generated by the input voltages representing values X1 to Xm and weights stored in the variable resistance cells to produce sum-of-products results for the selected vertical string.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/233,404Filed 27 Dec 2018 · continuation in part
Priority: 17 Jan 2018
Published: US 2019/0220249 A118 Jul 2019
Granted: 23 Mar 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification21 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G06F 7/388
Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal…:…
G06F 7/5443
For evaluating functions by calculation: sum of products
G06N 3/065
Using electronic means: analogue means

Family

Application15/873,369Parent of this continuation-in-part · filed 17 Jan 2018
Application15/887,166Parent of this continuation-in-part · filed 2 Feb 2018
Application62/753,726Us provisional application · filed 31 Oct 2018
US 2019/0221263 A1Pre-grant publication · published 18 Jul 2019
US 10,719,296 B2Parent of this continuation-in-part
US 2019/0220249 A1Published application
US 2019/0244662 A1Published application
US 10,957,392 B2This patent

From the US filing history. Foreign family members aren’t listed.