Memory devices and methods which may facilitate tensor memory access

An apparatus comprising:

• a memory array comprising a plurality of memory cells;
• and
• a memory controller coupled to the memory array and configured to:
• receive a memory command that comprises a memory access operation, a starting address for the memory access operation, and a dimension of a tensor for the memory access operation, wherein the memory access operation corresponds to a submatrix operation;
• generate a sequence of memory addresses for the memory access operation;
• associate a set of instructions to access a memory based on the generated sequence of memory addresses, the set of instructions includes a set of parameters associated with the command, the set of parameters comprising the starting address, an integer number indicating a type of the memory command, and a first length of data and a second length of data associated with the memory command for the memory access operation;
• and
• perform, according to the sequence of memory addresses, the memory access operation for data having a size that is based at least in part on the dimension of the tensor.

A method comprising:

• receiving a first read command associated with a first read operation;
• generating a first sequence of memory addresses for the first read operation based at least in part on the read command, wherein the first sequence of memory address indicates a starting address, a type of tensor or matrix dimension, a length of data, or combinations thereof;
• specifying a set of instructions to access a memory with the first sequence of memory addresses, the set of instructions includes a set of parameters associated with the read command, the set of parameters comprising the starting address, an integer number indicating a type of the read command, and the length of data associated with the type of the read command;
• reading data from a memory based at least in part on the first sequence of memory addresses, wherein the data is associated with the first sequence of memory addresses;
• writing the data to a buffer;
• receiving a second read command associated with a second read operation;
• determining that the second read operation is associated with a second sequence of memory addresses that is a same sequence of memory addresses utilized in the first read operation;
• reading the data stored in the buffer, the data associated with the second sequence of memory addresses, the data stored in the buffer based partly on the first sequence of memory addresses being utilized in the first read operation;
• and
• providing the data stored in the buffer to perform the second read operation.