Test scheduling and test access in test compression environment

A system, comprising:

• a computer comprising one or more processors and a non-transitory computer-readable medium storing executable instructions that, when executed by the one or more processors, cause the computer to perform operations, comprising:
• receiving test information, the test information comprising compressed test data that encode a plurality of test patterns for testing a plurality of cores in an integrated circuit and automatic test equipment (ATE) channel requirements for delivering the compressed test data to the plurality of cores;
• forming test pattern clusters based on the test information, the test pattern clusters including test patterns selected from the plurality of test patterns, wherein the selected test patterns are delivered to the plurality of cores in the integrated circuit in parallel, wherein forming at least one of the test pattern clusters comprises merging two configuration classes that comprise disjoint subsets of the plurality of cores in the integrated circuit;
• generating ATE channel allocation information for the plurality of cores in the integrated circuit based on the test pattern clusters;
• and
• designing a test access circuit comprising a rearrangeable interconnection network comprising wires connecting ATE channels to the plurality of cores in the integrated circuit, wherein the test access circuit is configured to:
• use the rearrangeable interconnection network to dynamically allocate the ATE channels to the plurality of cores in the integrated circuit using the ATE channel allocation information generated based on the test pattern clusters, and
• deliver a plurality of the test patterns in a test pattern cluster, of the test pattern clusters, to the plurality of cores in the integrated circuit in parallel.

A non-transitory processor-readable medium storing processor-executable instructions for causing one or more processors to perform a method of test scheduling in test compression environment, comprising:

• receiving test information, the test information comprising compressed test data that encode a plurality of test patterns for testing a plurality of cores in an integrated circuit and automatic test equipment (ATE) channel requirements for delivering the compressed test data to the plurality of cores, the test information further comprising correlated core information;
• forming test pattern clusters based on the test information, the test pattern clusters including test patterns selected from the plurality of test patterns, wherein the selected test patterns are delivered to the plurality of cores in the integrated circuit in parallel, wherein forming at least one of the test pattern clusters comprises merging two configuration classes that comprise disjoint subsets of the plurality of cores in the integrated circuit;
• generating ATE channel allocation information for the plurality of cores in the integrated circuit based on the test pattern clusters;
• and
• designing a test access circuit comprising a rearrangeable interconnection network comprising wires connecting ATE channels to the plurality of cores in the integrated circuit, wherein the test access circuit is configured to:
• use the rearrangeable interconnection network to dynamically allocate ATE channels to the plurality of cores in the integrated circuit using the ATE channel allocation information generated based on the test pattern clusters, and
• deliver a plurality of test patterns in a test pattern cluster, of the test pattern clusters, to the plurality of cores in the integrated circuit in parallel.