Multimode cryptographic processor
AssigneeFungible, Inc.
InventorsPhillip A. Thomas, Rajan Goyal, Eric Scot Swartzendruber
Life of this patent
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Abstract
This disclosure describes techniques that include performing cryptographic operations (encryption, decryption, generation of a message authentication code). Such techniques may involve the data processing unit performing any of multiple modes of encryption, decryption, and/or other cryptographic operation procedures or standards, including, Advanced Encryption Standard (AES) cryptographic operations. In some examples, the security block is implemented as a unified, multi-threaded, high-throughput encryption and decryption system for performing multiple modes of AES operations.
Claims30
A method comprising:
- accessing, by a device that includes a multistage Advanced Encryption Standard (AES) pipeline configured to perform AES cryptographic operations, mode selection data;
- identifying, by the device and based on the mode selection data, a selected AES mode from among a plurality of AES cryptographic operation modes capable of being performed by the device, wherein the plurality of AES cryptographic operation modes include at least one mode in which feedback is employed within the multistage AES pipeline;
- receiving, by the device, a plurality of sets of input data to be processed by a cryptographic operation associated with the selected AES mode;
- generating, by the device and from the plurality of sets of input data based on the selected AES mode, a plurality of sets of pipeline input data;
- processing, by the multistage AES pipeline using one or more cryptographic keys, each of the plurality of sets of pipeline input data concurrently using a plurality of threads to generate a plurality of sets of pipeline output data, wherein each of the plurality of sets of pipeline output data is generated by the multistage AES pipeline based on a respective one of the plurality of sets of pipeline input data;
- and
- generating, by the device and based on each of the plurality of sets of pipeline output data and the selected AES mode, a plurality of sets of mode output data, wherein each of the plurality of sets of mode output data corresponds to a respective one of the plurality of sets of input data after performing the cryptographic operation associated with the selected AES mode.
A device comprising:
- a plurality of key registers configured to receive a plurality of cryptographic keys;
- a multistage Advanced Encryption Standard (AES) pipeline configured to receive each of the plurality of cryptographic keys from the plurality of key registers;
- and
- control logic for feeding data into the AES pipeline and receiving data from the AES pipeline, wherein the control logic is configured to:
- access mode selection data,
- identify, based on the mode selection data, a selected AES mode from among a plurality of AES cryptographic operation modes capable of being performed by the device,
- receive a plurality of sets of input data to be processed by a cryptographic operation associated with the selected AES mode,
- generate, from the plurality of sets of input data based on the selected AES mode, a plurality of sets of pipeline input data using only a single thread of execution,
- cause the multistage AES pipeline to process, using one or more cryptographic keys, each of the plurality of sets of pipeline input data to generate a plurality of sets of pipeline output data, wherein each of the plurality of sets of pipeline output data is generated by the multistage AES pipeline based on a respective one of the plurality of sets of pipeline input data, and wherein the plurality of sets of pipeline output data are concurrently generated using a plurality of threads, and
- generate, based on each of the plurality of sets of pipeline output data and the selected AES mode, a plurality of sets of mode output data, wherein each of the plurality of sets of mode output data is one of the plurality of sets of input data after performing the cryptographic operation associated with the selected AES mode.
A device comprising:
- a plurality of key registers configured to receive a plurality of cryptographic keys;
- a multistage Advanced Encryption Standard (AES) pipeline configured to receive each of the plurality of cryptographic keys from the plurality of key registers, wherein the AES pipeline is a fourteen-stage AES pipeline;
- control logic for feeding data into the AES pipeline and receiving data from the AES pipeline, wherein the control logic is configured to:
- access mode selection data,
- identify, based on the mode selection data, a selected AES mode from among a plurality of AES cryptographic operation modes capable of being performed by the device,
- identify a length of the one or more cryptographic keys, and
- configure, based on the length of the one or more cryptographic keys, a plurality of the stages of the fourteen-stage AES pipeline as passthrough stages;
- receive a plurality of sets of input data to be processed by a cryptographic operation associated with the selected AES mode,
- generate, from the plurality of sets of input data based on the selected AES mode, a plurality of sets of pipeline input data,
- cause the multistage AES pipeline to process, using one or more cryptographic keys, each of the plurality of sets of pipeline input data to generate a plurality of sets of pipeline output data, wherein each of the plurality of sets of pipeline output data is generated by the multistage AES pipeline based on a respective one of the plurality of sets of pipeline input data, and wherein the plurality of sets of pipeline output data are concurrently generated using a plurality of threads, and
- generate, based on each of the plurality of sets of pipeline output data and the selected AES mode, a plurality of sets of mode output data, wherein each of the plurality of sets of mode output data is one of the plurality of sets of input data after performing the cryptographic operation associated with the selected AES mode.
Dependencies are inferred from the claim text.