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US 10,951,391 B2Granted
Randomized logic against side channel attacks
AssigneeBar-Ilan University
InventorsMoshe Avital, Itamar Levy, Osnat Keren, Alexander Fish
Life of this patent
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Abstract
A randomization element includes a logic input for inputting a logic signal, a logic output for outputting the input logic signal at a delay and a randomization element. The randomization elements introduces the delay between said logic input and said logic output and operates selectably in static mode and in dynamic mode in accordance with a mode control signal. A logic circuit may be formed with randomization elements interspersed amongst the logic gates, to obtain protection against side channel attacks by inputting a selected control sequence into the randomization elements.
Claims24
A randomization element comprising:
- a logic input, configured to input a logic signal;
- a logic output, configured to output said logic signal at a delay;
- and
- a delay element associated with said logic input and logic output, configured to introduce a delay between said logic input and said logic output, wherein said delay element operates selectably in static mode and in dynamic mode in accordance with a mode control signal,
- wherein said delay element comprises:
- a first two-to-one multiplexer, having a first input connected to a ground signal, a second input connected to a clock signal, an output and a control input connected to said mode control signal;
- and
- a second two-to-one multiplexer, having a first input connected to said logic input, a second input connected to a reference voltage, an output connected to said logic output and a respective control input connected to said output of said first two-to-one multiplexer,
- wherein said control input of said first two-to-one multiplexer selects between said first and said second inputs of said first two-to-one multiplexer for outputting at said output of said first two-to-one multiplexer, and wherein said control input of said second two-to-one multiplexer selects between said first and said second inputs of said second two-to-one multiplexer for outputting at said output of said second two-to-one multiplexer.
6 more elements
A logic circuit, comprising:
- a plurality of logic gates;
- a plurality of randomization elements interspersed between said logic gates, each of said randomization elements being configured to introduce a delay between a logic output of a respective preceding logic gate and a logic input of a respective following logic gate, wherein each of said randomization elements operates selectably in static mode and in dynamic mode in accordance with a respective mode control signal;
- and
- a control sequence provider associated with said randomization elements, configured to provide sequences of control signals to said randomization elements, wherein said sequences are selected to shape a logic circuit power profile and logic signal propagation timing during logic circuit operation, so as to combat side channel attacks,
- wherein at least one of said randomization elements comprises:
- a first two-to-one multiplexer, having a first input connected to a ground signal, a second input connected to a clock signal, an output and a control input connected to said mode control signal;
- and
- a second two-to-one multiplexer, having a first input connected to a logic output of a preceding logic gate, a second input connected to a reference voltage, an output connected to a logic input of a following logic gate, and a respective control input connected to said output of said first two-to-one multiplexer,
- wherein said control input of aid first two-to-one multiplexer selects between said first and said second inputs of said first two-to-one multiplexer for outputting at said output of said first two-to-one multiplexer, and wherein said control input of said second two-to-one multiplexer selects between said first and said second inputs of said second two-to-one multiplexer for outputting at said output of said second two-to-one multiplexer.
6 more elements
A method for combating side channel attacks on a logic circuit, comprising:
- providing a logic circuit, wherein said logic circuit comprises:
- a plurality of logic gates;
- and
- a plurality of randomization elements interspersed between said logic gates, each of said randomization elements introducing a delay between a logic output of a respective preceding logic gate and a logic input of a respective following logic gate, wherein each of said randomization elements operates selectably in static mode and in dynamic mode in accordance with a respective control signal and wherein a respective delay of each of said randomization elements is controlled by a timing of a respective clock signal;
- selecting a sequence of control signals to shape a logic circuit power profile and logic signal propagation timing during logic circuit operation so as to combat side channel attacks;
- and
- inputting said sequence of control signals to said randomization elements, wherein at least one of said randomization elements comprises:
- a first two-to-one multiplexer, having a first input connected to a ground signal, a second input connected to a respective clock signal, an output and a control input connected to a respective control signal;
- and
- a second two-to-one multiplexer, having a first input connected to a logic output of a respective preceding logic gate, a second input connected to a reference voltage, an output connected to a logic input of a respective following logic gate, and a control input connected to said output of said first two-to-one multiplexer,
- wherein said control input of said first two-to-one multiplexer selects between said first and said second inputs of said first two-to-one multiplexer for outputting at said output of said first two-to-one multiplexer, and wherein said control input of said second two-to-one multiplexer selects between said first and said second inputs of said second two-to-one multiplexer for outputting at said output of said second two-to-one multiplexer.
8 more elements
Dependencies are inferred from the claim text.