Low density parity check decoder

A method for decoding a low density parity check (LDPC) code, comprising:

• combining an R message from a previous iteration with a P message to produce a Q message using a Q message generator;
• adding the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message using a P sum adder array;
• and
• processing a quasi-cyclic LDPC parity check matrix.

A low density parity check (LDPC) code decoder, comprising:

• a Q message generator;
• and
• circuitry configured to route, to the Q message generator:
• a P message generated for a layer of an LDPC parity check matrix processed prior to a most recently processed layer of the LDPC parity check matrix for use with a first block of a currently processed layer of the LDPC parity check matrix;
• wherein the first block is dependent on a result of the most recently processed layer that is unavailable at a time that the first block is being processed;
• and
• wherein the circuitry comprises an array of final state register banks, each bank comprising a plurality of registers for storing final state data for a layer of the LDPC parity check matrix.

A low density parity check (LDPC) decoder, comprising:

• a Q message generator;
• circuitry configured to route, to the Q message generator:
• a P message generated for a first non-zero block of an LDPC matrix for use with a second non-zero block of the LDPC matrix based on a P message from a third non-zero block being unavailable at a time that the second non-zero block is being processed;
• wherein the first non-zero block, the second non-zero block and the third non-zero block are in a same block column of the LDPC matrix;
• and the third non-zero block is an only non-zero block between the first non-zero block and the second non-zero block in the block column;
• and
• wherein the circuitry is further configured to select one of an updated P message and a channel log-likelihood ratio (LLR) for storage in a P memory, wherein the circuitry is configured to select the channel LLR to initialize decoding.

A low density parity check (LDPC) code decoder, comprising:

• LDPC decoding circuitry comprising:
• an array of reconfigurable minimum finder units adapted to:
• selectably process a first plurality (K1) of edges of a first plurality (M1) of check nodes of a first LDPC matrix;
• selectably process a second plurality (K2) of edges of a second plurality (M2) of check nodes of a second LDPC matrix;
• wherein:
• K1 is less than K2;
• M1 is greater than M2;
• and
• K1*M1=K2*M2;
• and
• wherein the circuitry comprises an array of final state register banks, each bank comprising a plurality of registers for storing final state data for a layer of one of the first LDPC matrix and the second LDPC matrix.

A low density parity check (“LDPC”) code decoder, comprising:

• a first R computation circuit configured to compute a first R message based on at least a message index value read from a first memory;
• a second memory that stores a first Q message;
• a P message generator that combines a second R message with the first Q message read from the second memory to produce a P message;
• a router for the P message;
• and
• a Q message generator that combines the P message and the first R message to provide a second Q message;
• wherein the router is a cyclic shifter.

A low density parity check (LDPC) code decoder, comprising:

• a control unit that controls decoder processing, the control unit configured to cause the decoder to process blocks of a quasi-cyclic LDPC parity check matrix in a first sequence wherein the first sequence specifies a first set of blocks of a given layer to be processed at a given time and a second set of blocks of the given layer to be processed after the first set of blocks;
• wherein the first set specifies only blocks of the given layer that are not dependent on a result of a previously processed layer and the second set specifies blocks of the given layer that are dependent on a result of the previously processed layer;
• and
• wherein the decoder is configured to decode using the quasi-cyclic LDPC parity check matrix.

A method for decoding a low density parity check (LDPC) code, comprising:

• computing a first R message based on at least a message index value read from a first memory;
• storing a first Q message in a second memory;
• combining a second R message with the first Q message read from the second memory to produce a P message;
• routing the P message using a cyclic shifter;
• and combining the P message and the first R message to provide a second Q message.