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US 10,951,232 B2Granted
Error correction bit flipping scheme
AssigneeMicron Technology, Inc.
InventorJongtae Kwak
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).
Claims16
A method, comprising:
- receiving, at a flip decision component, an error corrected flip bit directly from a flip bit error correction component via a first output line;
- receiving, at the flip decision component from a data bit error correction component configured to perform a bit error correction procedure, one or more data bits via a second output line;
- and
- determining, at the flip decision component, whether to invert the one or more data bits based at least in part on receiving the error corrected flip bit and receiving the one or more data bits.
1 more element
A method, comprising:
- receiving, at a flip decision component, an error corrected flip bit directly from a flip bit error correction component via a first output line;
- receiving, at the flip decision component from a data bit error correction component, one or more data bits via a second output line;
- and
- determining, at the flip decision component, whether to invert the one or more data bits based at least in part on receiving the error corrected flip bit and receiving the one or more data bits;
- determining, at the flip decision component, an output value using a configured logic criterion based at least in part on receiving the one or more data bits and the error corrected flip bit;
- and
- transmitting an indicator of the output value to a data bus decision component, wherein determining, at the flip decision component, the output value using the configured logic criterion comprises:
- comparing the received data bits to the configured logic criterion to determine whether a number of logic states of the received data bits of a first type are greater than a threshold.
5 more elements
An apparatus, comprising:
- a flip decision component;
- a flip bit error correction component coupled with the flip decision component and configured to transmit one or more flip bits directly to the flip decision component over a first output line coupling the flip bit error correction component and the flip decision component;
- and
- a data bit error correction component coupled with the flip decision component and configured to:
- perform a bit error correction procedure;
- and
- transmit one or more data bits to the flip decision component over a second output line based at least in part on performing the bit error correction procedure.
4 more elements
An apparatus, comprising:
- a flip decision component;
- a flip bit error correction component coupled with the flip decision component and configured to transmit one or more flip bits directly to the flip decision component over a first output line coupling the flip bit error correction component and the flip decision component;
- and
- a data bit error correction component coupled with the flip decision component and configured to transmit one or more data bits to the flip decision component over a second output line, wherein the flip decision component comprises:
- stored logic criterion configured to output a data bit inversion decision indicating whether to invert the one or more data bits, the apparatus further comprising:
- a data bus decision component, coupled with the flip decision component, configured to receive from the flip decision component, wherein the flip decision component is configured to:
- compare the received data bits to the stored logic criterion to determine that a number of logic states of the received data bits of a first type satisfies a threshold;
- and
- output an indication that the number of logic states of the received data bits of the first type satisfies the threshold.
6 more elements
Dependencies are inferred from the claim text.