Successive approximation register analog-to-digital converter with multiple sample capacitors

A method comprising, in a successive approximation register analog-to-digital converter (SAR ADC) having a plurality of capacitor networks, wherein each capacitor network of the plurality of capacitor networks has a sampling capacitor and at least one non-sampling capacitor;

• sampling, with each sampling capacitor, an analog input signal to the SAR ADC;
• comparing the sampled analog input signal of the SAR ADC to an output of a digital-to-analog converter (DAC), wherein the DAC comprises a plurality of sub-DACs including at least:
• a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks;
• and
• a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks;
• responsive to comparing the sampled analog input signal to the output of the DAC, communicating, with a successive approximation register (SAR) to the DAC successive approximations of a digital code corresponding to the sampled analog input signal;
• and
• operating each particular capacitor network of the plurality of capacitor networks in a plurality of phases comprising:
• a sampling phase in which the particular capacitor network is decoupled from the DAC and samples the analog input signal using its respective sampling capacitor;
• and
• a conversion phase in which the particular capacitor is coupled to the DAC and converts, using successive approximation, a sampled analog input signal sampled during the sampling phase into an equivalent digital output signal.

A system comprising:

• an analog front end configured to generate an analog input signal;
• and
• a successive approximation register analog-to-digital converter (SAR ADC) configured to convert the analog input signal to an equivalent digital signal comprising:
• a plurality of capacitor networks, wherein each capacitor network of the plurality of capacitor networks has a sampling capacitor for sampling the analog input signal to the SAR ADC and at least one non-sampling capacitor;
• a digital-to-analog converter (DAC) comprising a plurality of sub-DACs including at least:
• a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks;
• and
• a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks;
• an analog comparator configured to compare a sampled analog input signal of the SAR ADC to an output of the DAC;
• and
• a successive approximation register (SAR) configured to, responsive to an output of the analog comparator, communicate to the DAC successive approximations of a digital code corresponding to the sampled analog input signal;
• wherein each particular capacitor network of the plurality of capacitor networks is configured to operate in a plurality of phases comprising:
• a sampling phase in which the particular capacitor network is decoupled from the DAC and samples the analog input signal using its respective sampling capacitor;
• and
• a conversion phase in which the particular capacitor is coupled to the DAC and converts, using successive approximation, a sampled analog input signal sampled during the sampling phase into an equivalent digital output signal.