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US 10,951,221 B2Granted
Testing an analog-to-digital converter using counters
AssigneeRegents of the University of Minnesota
InventorsGyusung Park, Hyung-il Kim
Life of this patent
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Abstract
In some examples, a device includes an analog-to-digital converter (ADC) configured to receive an analog signal and output digital codes based on values of the analog signal. The device also includes a plurality of counters, where each counter of the plurality of counters is configured to increment in response to a respective digital code outputted by the ADC.
Claims20
A device comprising:
- an analog-to-digital converter (ADC) configured to receive an analog signal and output digital codes based on values of the analog signal;
- a plurality of counters, wherein each counter of the plurality of counters is configured to increment in response to a respective digital code outputted by the ADC;
- and
- an interleaving controller configured to:
- determine that a particular bit of a first digital code outputted by the ADC matches a control bit;
- and
- cause a respective counter of the plurality of counters to increment in response to determining that the particular bit of the first digital code matches the control bit.
4 more elements
A method comprising:
- receiving, at an analog-to-digital converter (ADC), an analog signal during non-linearity testing;
- outputting, by the ADC, digital codes based on values of the analog signal during the non-linearity testing;
- determining, by an interleaving controller, that a particular bit of a first digital code outputted by the ADC matches a control bit;
- causing, by the interleaving controller, a respective counter of a plurality of counters to increment in response to determining that the particular bit of the first digital code matches the control bit;
- and
- incrementing the respective counter in response to determining that the particular bit the first digital code matches the control bit.
3 more elements
A device comprising:
- a plurality of counters, wherein each counter of the plurality of counters is configured to increment in response to a respective digital code outputted by an analog-to-digital converter (ADC) during non-linearity testing;
- and
- a scan-out circuit configured to output counts stored by the plurality of counters during a pause in the non-linearity testing.
Dependencies are inferred from the claim text.