Synchronization of clock signals generated using output dividers

A clock generator comprising:

• a loop filter configured to generate a filtered phase difference signal based on a reference clock signal and a feedback clock signal;
• a first output divider configured to generate a first output clock signal responsive to an input clock signal and a first divider control signal based on the filtered phase difference signal and configured to generate a first time code based on a counter signal and a first update of the first output clock signal in response to an update of the filtered phase difference signal to a first value from a second value, the feedback clock signal being based on the first output clock signal;
• a second output divider configured to generate a second output clock signal responsive to the input clock signal, a second divider control signal, and a correction signal, the second divider control signal being based on the filtered phase difference signal, and configured to generate a second time code based on the counter signal and a second update of the second output clock signal in response to the update of the filtered phase difference signal;
• and
• an error correction circuit configured to generate the correction signal based on the first time code, the second time code, the first value, and the second value.