Majority logic gate fabrication

A method of forming a majority gate, the method comprising:

• forming first source and drain regions of a first transistor in a substrate, wherein the first source region is coupled to ground;
• forming second source and drain regions of a second transistor in the substrate, wherein the second source region is coupled to the ground;
• forming a first interconnect of a first metal layer over the first transistor;
• forming a first via coupled to the first drain region and the first interconnect;
• forming a second via coupled to the second drain region and a second interconnect of the first metal layer;
• forming first, second, and third non-ferroelectric capacitors on the first interconnect;
• forming a fourth capacitor with non-linear polar material, the fourth capacitor on the first interconnect;
• forming a third via coupled to the second interconnect;
• forming a third interconnect coupled to the first non-ferroelectric capacitor, wherein the third interconnect is of a second metal layer, wherein the second metal layer is orthogonal to the first metal layer;
• forming a fourth interconnect coupled to the second non-ferroelectric capacitor, wherein the fourth interconnect is of the second metal layer;
• forming a fifth interconnect coupled to the third non-ferroelectric capacitor, wherein the fifth interconnect is of the second metal layer;
• and
• forming a sixth interconnect coupled to the fourth capacitor and the third via, wherein the sixth interconnect is of the second metal layer.

A system comprising:

• a processor;
• a communication interface communicatively coupled to the processor;
• and
• a memory coupled to the processor, wherein the processor comprises a majority gate logic which includes:
• first source and drain regions of a first transistor in a substrate, wherein the first source region is coupled to ground;
• second source and drain regions of a second transistor in the substrate, wherein the second source region is coupled to the ground;
• a first interconnect of a first metal layer over the first transistor;
• a first via coupled to the first drain region and the first interconnect;
• a second via coupled to the second drain region and a second interconnect of the first metal layer;
• first, second, and third non-ferroelectric capacitors on the first interconnect;
• a fourth capacitor with non-linear polar material, the fourth capacitor on the first interconnect;
• a third via coupled to the second interconnect;
• a third interconnect coupled to the first non-ferroelectric capacitor, wherein the third interconnect is of a second metal layer, wherein the second metal layer is orthogonal to the first metal layer;
• a fourth interconnect coupled to the second non-ferroelectric capacitor, wherein the fourth interconnect is of the second metal layer;
• a fifth interconnect coupled to the third non-ferroelectric capacitor, wherein the fifth interconnect is of the second metal layer;
• and
• a sixth interconnect coupled to the fourth capacitor and the third via, wherein the sixth interconnect is of the second metal layer, wherein the processor includes logic coupled an output of the majority logic gate.