Self-timed processors implemented with multi-rail null convention logic and unate gates

A self-timed processor comprising:

• a plurality of functional blocks comprising multi-rail null convention logic, each of the functional blocks to output one or more multi-rail data values that each alternate between a valid state and a null state, and
• a global acknowledge tree to generate a global acknowledge signal provided to all of the plurality of functional blocks, wherein the global acknowledge signal switches to a null state when all of the one or more multi-rail data values output from all of the plurality of functional blocks are in the null state, wherein each of the plurality of functional blocks further comprises:
• a register to receive the global acknowledge signal from the global acknowledge tree;
• and
• combinatorial logic to output the one or more multi-rail data values to the register,
• wherein the combinatorial logic of at least one of the plurality of functional blocks comprises one or more non-threshold, Boolean gates that include AND gates and OR gates.