Flip flop standard cell
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsNick Samra, Stefan Rusu, Ta-Pen Guo
Life of this patent
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Abstract
A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.
Claims20
A flip flop standard cell, comprising:
- a data input terminal;
- clock input terminal configured to receive a clock signal;
- a data output terminal;
- a latch;
- a bit write circuit configured to receive a bit write signal, wherein a second data signal received on the data input terminal is latched and provided at the output terminal in response to the bit write signal and the clock signal;
- and
- a hold circuit configured to receive a hold signal, wherein a first data signal received on the data input terminal prior to the second data signal is provided at the output terminal, and the second data signal received on the data input terminal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.
A memory device, comprising:
- a plurality of flip flop standard cells, each including a data input terminal, a clock input terminal, a bit write terminal, and a data output terminal;
- a first driver circuit configured to output a clock signal and an inverted clock signal to the clock input terminal of each of the plurality of flip flop standard cells;
- a second driver circuit configured to output a bit write signal to the bit write terminal of each of the plurality of flip flop standard cells;
- and
- wherein each of the plurality of flip flop standard cells is configured to latch a first data signal received at the data input terminal in response to the received clock and bit write signals.
A method, comprising:
- providing a plurality of flip flop standard cells, each including a data input terminal, a hold terminal, a clock terminal, and a data output terminal;
- latching a first data signal into each of the plurality of flip flop standard cells;
- providing the first data signal at the data output terminals of the plurality of flip flop cells;
- sending a clock signal and an inverted clock signal to the clock input terminal of each of the plurality of flip flop standard cells;
- sending a hold signal to the hold terminal of each of the plurality of flip flop standard cells;
- receiving a second data signal at the data input terminal of each of the flip flop standard cells;
- continuing to latch the first data signal into each of the plurality of flip flop standard cells in response to the hold signal;
- and
- continuing to provide the first data signal at the data output terminals of the plurality of flip flop standard cells in response to the hold signal.
Dependencies are inferred from the claim text.