Clock circuit and method of operating the same

A clock circuit, comprising:

• a latch circuit configured to latch an enable signal, and to generate a latch output signal based on at least a first clock signal;
• a memory state latch circuit coupled to the latch circuit, and configured to generate an output clock signal responsive to a control signal;
• a memory state trigger circuit coupled to at least the memory state latch circuit, and configured to adjust the output clock signal responsive to at least the latch output signal;
• a clock trigger circuit coupled to the latch circuit and the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal and a third clock signal, and configured to control the latch circuit and the memory state trigger circuit based on at least the first clock signal, the first clock signal being inverted from the second clock signal;
• and
• a level shifter circuit coupled to the memory state trigger circuit and the clock trigger circuit, and configured to generate the third clock signal from the second clock signal.

A method of operating a clock circuit, the method comprising:

• causing, by a latch circuit, a latch output signal to transition from a first voltage level to a second voltage level different from the first voltage level;
• causing a clock trigger circuit to pull a first node from the second voltage level to the first voltage level in response to a transition of a first clock signal from the first voltage level to the second voltage level and a transition of a second clock signal from the first voltage level to a third voltage level different from the second voltage level, the first clock signal having a first voltage swing, the second clock signal having a second voltage swing different from the first voltage swing, the causing the clock trigger circuit to pull the first node thereby causing a first control signal of the clock trigger circuit to transition from the second voltage level to the first voltage level, the clock trigger circuit being coupled to at least an input of the latch circuit or an input of a memory state trigger circuit by the first node, and the first control signal being fed back from the clock trigger circuit to the input of the latch circuit from the first node;
• and
• causing, by the memory state trigger circuit, an output clock signal to transition from the second voltage level to the first voltage level in response to the transition of the first clock signal to the second voltage level, in response to the transition of the second clock signal to the third voltage level, and in response to the transition of the latch output signal to the third voltage level.