Timing data acquisition device that supports efficient set-up and hold time determination in synchronous systems

Abstract

A timing data acquisition device includes a data signal generator, which is configured to generate a plurality of data signals by repeatedly delaying a first periodic timing signal in increments of a first delay value, and a clock signal generator, which is configured to generate a plurality of clock signals by repeatedly delaying a second periodic timing signal in increments of a second delay value exceeding the first delay value. A plurality of D flip-flops are also provided. The flip-flops have: (i) data terminals responsive to respective ones of the plurality of data signals, and (ii) clock terminals responsive to respective ones of the plurality of clock signals. The flip flops are configured to generate a plurality of latched output signals having values that collectively encode at least one of a set-up time and a hold-time of a semiconductor device by identifying a pass/fail boundary point between the delays associated with the plurality of data signals and the delays associated with the plurality of clock signals.

Dependencies are inferred from the claim text.