Semiconductor integrated circuit, transmission device, and memory device

A transmission device comprising:

• a first terminal configured to be electrically connectable to a semiconductor memory device;
• a second terminal configured to be electrically connectable to the semiconductor memory device;
• a clock supply circuit configured to be able to output a first clock and a second clock, the first clock having a first period, the second clock having a second period that is 1/m times the first period, where m is a natural number of 2 or more;
• a first output circuit configured to output a first signal indicating content of data to the first terminal when a first operation is performed and output a second signal having a toggle pattern based on the first clock to the first terminal when a second operation is performed;
• and
• a second output circuit configured to output an operation clock based on the first clock to the second terminal when the first operation is performed and output a sampling clock based on the second clock to the second terminal when the second operation is performed.

A memory device comprising:

• a first semiconductor memory device;
• a first terminal electrically connected to the first semiconductor memory device;
• a second terminal electrically connected to the first semiconductor memory device;
• a clock supply circuit configured to be able to output a first clock and a second clock, the first clock having a first period, the second clock having a second period that is 1/m times the first period, where m is a natural number of 2 or more;
• a first output circuit configured to output a first signal indicating content of data to the first terminal when a first operation is performed and output a second signal having a toggle pattern based on the first clock to the first terminal when a second operation is performed;
• a second output circuit configured to output an operation clock based on the first clock to the second terminal when the first operation is performed and output a sampling clock based on the second clock to the second terminal when the second operation is performed;
• and
• a control circuit configured to issue a first command to read a sampling result, which has been obtained by performing detection for the second signal using the sampling clock in the first semiconductor memory device and stored in the first semiconductor memory device, from the first semiconductor memory device.