US 10,951,185 B2Granted

Differential amplifier circuit and serial transmission circuit

AssigneeToshiba Memory Corporation

InventorShinsuke Fujii

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Abstract

A differential amplifier circuit has a first current circuit comprising a first transistor and a second transistor, and to flow a current depending on a voltage of a first input signal, a second current circuit comprising a third transistor and a fourth transistor, and to flow a current depending on a voltage of a second input signal, a fifth transistor comprising a gate connected to a gate and the drain of the second transistor, and to flow a current that is M times greater than the current flowing between the drain and the source of the second transistor, and a sixth transistor comprising a gate connected to a gate and the drain of the fourth transistor and cascode-connected to the first transistor, and to flow a current that is N times greater than the current flowing between the drain and the source of the fourth transistor.

Claims20

Dependent claims

A differential amplifier circuit comprising:

a first circuit comprising a first transistor and a second transistor cascode-connected, and configured to flow a current that depends on a voltage of a first input signal being one of differential input signals, between a drain and a source of the first transistor and between a drain and a source of the second transistor;
a second circuit comprising a third transistor and a fourth transistor cascode-connected, and configured to flow a current that depends on a voltage of a second input signal being another of the differential input signals, between a drain and a source of the third transistor and between a drain and a source of the fourth transistor;
a fifth transistor comprising a gate connected to a gate and the drain of the second transistor and cascode-connected to the third transistor, and configured to flow a current that is M times by current flowing between the drain and the source of the second transistor, between a drain and a source of the fifth transistor, where M is a real number that is greater than 0;
and
a sixth transistor comprising a gate connected to a gate and the drain of the fourth transistor and cascode-connected to the first transistor, and configured to flow a current that is N times by current flowing between the drain and the source of the fourth transistor, between a drain and a source of the sixth transistor, where N is a real number that is greater than 0,
wherein the source of the first transistor, the source of the second transistor, and the source of the sixth transistor are connected to one another,
the source of the third transistor, the source of the fourth transistor, and the source of the fifth transistor are connected to one another,
wherein differential output signals are output from at least one of a pair of the drain of the first transistor and the drain of the third transistor and a pair of the drain of the fifth transistor and the drain of the sixth transistor.

5 more elements

A differential amplifier circuit comprising:

a first circuit comprising a first transistor, and configured to flow a current that depends on a voltage of a first input signal being one of differential input signals, between a drain and a source of the first transistor;
a second transistor configured to flow a current that correlates with current flowing between the drain and the source of the first transistor, between a drain and a source of the second transistor;
a second circuit comprising a third transistor and configured to flow a current that depends on a voltage of a second input signal being another of the differential input signals, between a drain and a source of the third transistor;
a fourth transistor configured to flow a current that correlates with current flowing between the drain and the source of the third transistor, between a drain and a source of the fourth transistor;
a fifth transistor comprising a gate connected to a gate and the drain of the second transistor, and configured to flow a current that is M times by current flowing between the drain and the source of the second transistor, between the drain and a source of the fifth transistor, where M is a real number greater than 0;
and
a sixth transistor comprising a gate connected to a gate and the drain of the fourth transistor, and configured to flow a current that is N times by current flowing between the drain and the source of the fourth transistor, between the drain and a source of the sixth transistor, where N is a real number greater than 0,
wherein the source of the first transistor, the source of the second transistor, and the source of the sixth transistor are connected to one another,
the source of the third transistor, the source of the fourth transistor, and the source of the fifth transistor are connected to one another,
wherein differential output signals are output from at least one of a pair of the drain of the first transistor and the drain of the third transistor and a pair of the drain of the fifth transistor and the drain of the sixth transistor.

7 more elements

A serial transmission circuit comprising:

a transmitter configured to convert parallel data to differentiated serial data and output the serial data;
a transmission path configured to transmit the serial data output from the transmitter;
and
a receiver configured to receive the serial data transmitted via the transmission path and to convert the serial data to the parallel data,
the receiver comprising:
a differential amplifier circuit configured to change an output common-mode voltage of the differential input signals based on the serial data transmitted via the transmission path;
a clock data recovery circuit configured to separate a clock signal from the serial data based on differential output signals output from the differential amplifier circuit;
and
a parallel converter configured to convert the serial data to the parallel data in synchronization with the clock signal separated at the clock data recovery circuit, and
the differential amplifier circuit comprising:
a first circuit comprising a first transistor and a second transistor cascode-connected, and configured to flow a current that depends on a voltage of a first input signal being one of differential input signals, between a drain and a source of the first transistor and between a drain and a source of the second transistor;
a second circuit comprising a third transistor and a fourth transistor cascode-connected, and configured to flow a current that depends on a voltage of a second input signal being another of the differential input signals, between a drain and a source of the third transistor and between a drain and a source of the fourth transistor;
a fifth transistor comprising a gate connected to a gate and the drain of the second transistor and cascode-connected to the third transistor, and configured to flow a current that is M times by current flowing between the drain and the source of the second transistor, between a drain and a source of the fifth transistor, where M is a real number that is greater than 0;
and
a sixth transistor comprising a gate connected to a gate and the drain of the fourth transistor and cascode-connected to the first transistor, and configured to flow a current that is N times by current flowing between the drain and the source of the fourth transistor, between a drain and a source of the sixth transistor, where N is a real number that is greater than 0,
wherein the source of the first transistor, the source of the second transistor, and the source of the sixth transistor are connected to one another,
the source of the third transistor, the source of the fourth transistor, and the source of the fifth transistor are connected to one another,
wherein differential output signals are output from at least one of a pair of the drain of the first transistor and the drain of the third transistor and a pair of the drain of the fifth transistor and the drain of the sixth transistor.

15 more elements

A serial transmission circuit comprising:

a transmitter configured to convert parallel data to differentiated serial data and output the serial data;
a transmission path configured to transmit the serial data output from the transmitter;
and
a receiver configured to receive the serial data transmitted via the transmission path and to convert the serial data to the parallel data,
the receiver comprising:
a differential amplifier circuit configured to change an output common-mode voltage of the differential input signals based on the serial data transmitted via the transmission path;
a clock data recovery circuit configured to separate a clock signal from the serial data based on differential output signals output from the differential amplifier circuit;
and
a parallel converter configured to convert the serial data to the parallel data in synchronization with the clock signal separated at the clock data recovery circuit, and
the differential amplifier circuit comprising:
a first circuit comprising a first transistor, and configured to flow a current that depends on a voltage of a first input signal being one of differential input signals, between a drain and a source of the first transistor;
a second transistor configured to flow a current that correlates with current flowing between the drain and the source of the first transistor, between a drain and a source of the second transistor;
a second circuit comprising a third transistor and configured to flow a current that depends on a voltage of a second input signal being another of the differential input signals, between a drain and a source of the third transistor;
a fourth transistor configured to flow a current that correlates with current flowing between the drain and the source of the third transistor, between a drain and a source of the fourth transistor;
a fifth transistor comprising a gate connected to a gate and the drain of the second transistor, and configured to flow a current that is M times by current flowing between the drain and the source of the second transistor, between the drain and a source of the fifth transistor, where M is a real number greater than 0;
and
a sixth transistor comprising a gate connected to a gate and the drain of the fourth transistor, and configured to flow a current that is N times by current flowing between the drain and the source of the fourth transistor, between the drain and a source of the sixth transistor, where N is a real number greater than 0,
wherein the source of the first transistor, the source of the second transistor, and the source of the sixth transistor are connected to one another,
the source of the third transistor, the source of the fourth transistor, and the source of the fifth transistor are connected to one another,
wherein differential output signals are output from at least one of a pair of the drain of the first transistor and the drain of the third transistor and a pair of the drain of the fifth transistor and the drain of the sixth transistor.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/296,628Filed 8 Mar 2019
Priority: JP JP2018-17165813 Sep 2018
Published: US 2020/0091882 A119 Mar 2020
Granted: 16 Mar 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03F 3/45094
Long tailed pairs: folded cascode stages
H03F 3/45183
Using MOSFET transistors as the active amplifying circuit: long tailed pairs
H03F 3/45179
Characterised by the way of implementation of the active amplifying circuit in the differential amplifier: using MOSFET transistors as the active…
H03F 2203/45028
Indexing scheme relating to differential amplifiers: the differential amplifier amplifying transistors are folded cascode coupled transistors